[08:39:15.357] <TB1> INFO: *** Welcome to pxar ***
[08:39:15.357] <TB1> INFO: *** Today: 2015/09/03
[08:39:15.357] <TB1> INFO: readRocDacs: /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C15.dat
[08:39:15.358] <TB1> INFO: readTbmDacs: /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//tbmParameters_C0b.dat
[08:39:15.358] <TB1> INFO: readMaskFile: /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//defaultMaskFile.dat
[08:39:15.358] <TB1> INFO: readTrimFile: /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters_C15.dat
[08:39:15.423] <TB1> INFO: clk: 4
[08:39:15.423] <TB1> INFO: ctr: 4
[08:39:15.423] <TB1> INFO: sda: 19
[08:39:15.423] <TB1> INFO: tin: 9
[08:39:15.423] <TB1> INFO: level: 15
[08:39:15.423] <TB1> INFO: triggerdelay: 0
[08:39:15.423] <TB1> QUIET: Instanciating API for pxar prod-10
[08:39:15.423] <TB1> INFO: Log level: INFO
[08:39:15.430] <TB1> INFO: Found DTB DTB_WXBYFL
[08:39:15.439] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[08:39:15.443] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[08:39:15.446] <TB1> INFO: RPC call hashes of host and DTB match: 397073690
[08:39:16.969] <TB1> INFO: DUT info:
[08:39:16.969] <TB1> INFO: The DUT currently contains the following objects:
[08:39:16.969] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[08:39:16.969] <TB1> INFO: TBM Core alpha (0): 7 registers set
[08:39:16.969] <TB1> INFO: TBM Core beta (1): 7 registers set
[08:39:16.969] <TB1> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[08:39:16.969] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.969] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.970] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.970] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.970] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:16.970] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[08:39:17.371] <TB1> INFO: enter 'restricted' command line mode
[08:39:17.371] <TB1> INFO: enter test to run
[08:39:17.371] <TB1> INFO: test: pretest no parameter change
[08:39:17.371] <TB1> INFO: running: pretest
[08:39:17.378] <TB1> INFO: ######################################################################
[08:39:17.378] <TB1> INFO: PixTestPretest::doTest()
[08:39:17.378] <TB1> INFO: ######################################################################
[08:39:17.380] <TB1> INFO: ----------------------------------------------------------------------
[08:39:17.380] <TB1> INFO: PixTestPretest::programROC()
[08:39:17.380] <TB1> INFO: ----------------------------------------------------------------------
[08:39:35.402] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[08:39:35.402] <TB1> INFO: IA differences per ROC: 20.1 19.3 20.9 20.1 17.7 20.1 20.1 20.1 17.7 18.5 20.1 16.1 19.3 20.1 19.3 20.1
[08:39:35.489] <TB1> INFO: ----------------------------------------------------------------------
[08:39:35.489] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[08:39:35.489] <TB1> INFO: ----------------------------------------------------------------------
[08:39:55.095] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[08:39:55.100] <TB1> INFO: ----------------------------------------------------------------------
[08:39:55.100] <TB1> INFO: PixTestPretest::findWorkingPixel()
[08:39:55.100] <TB1> INFO: ----------------------------------------------------------------------
[08:39:55.240] <TB1> INFO: Expecting 231680 events.
[08:40:04.500] <TB1> INFO: 231680 events read in total (8540ms).
[08:40:04.566] <TB1> INFO: Test took 9461ms.
[08:40:04.822] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[08:40:04.873] <TB1> INFO: ----------------------------------------------------------------------
[08:40:04.873] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[08:40:04.873] <TB1> INFO: ----------------------------------------------------------------------
[08:40:05.014] <TB1> INFO: Expecting 231680 events.
[08:40:14.288] <TB1> INFO: 231680 events read in total (8557ms).
[08:40:14.291] <TB1> INFO: Test took 9411ms.
[08:40:14.631] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[08:40:14.631] <TB1> INFO: CalDel: 145 162 159 158 144 137 159 149 156 138 143 158 142 171 156 130
[08:40:14.631] <TB1> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[08:40:14.634] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C0.dat
[08:40:14.634] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C1.dat
[08:40:14.634] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C2.dat
[08:40:14.634] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C3.dat
[08:40:14.634] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C4.dat
[08:40:14.634] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C5.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C6.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C7.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C8.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C9.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C10.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C11.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C12.dat
[08:40:14.635] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C13.dat
[08:40:14.636] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C14.dat
[08:40:14.636] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters_C15.dat
[08:40:14.636] <TB1> INFO: write tbm parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//tbmParameters_C0a.dat
[08:40:14.636] <TB1> INFO: write tbm parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//tbmParameters_C0b.dat
[08:40:14.636] <TB1> INFO: PixTestPretest::doTest() done, duration: 57 seconds
[08:40:14.769] <TB1> INFO: enter test to run
[08:40:14.769] <TB1> INFO: test: fulltest no parameter change
[08:40:14.769] <TB1> INFO: running: fulltest
[08:40:14.769] <TB1> INFO: ######################################################################
[08:40:14.769] <TB1> INFO: PixTestFullTest::doTest()
[08:40:14.769] <TB1> INFO: ######################################################################
[08:40:14.771] <TB1> INFO: ######################################################################
[08:40:14.771] <TB1> INFO: PixTestAlive::doTest()
[08:40:14.771] <TB1> INFO: ######################################################################
[08:40:14.772] <TB1> INFO: ----------------------------------------------------------------------
[08:40:14.772] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:40:14.772] <TB1> INFO: ----------------------------------------------------------------------
[08:40:15.095] <TB1> INFO: Expecting 41600 events.
[08:40:19.478] <TB1> INFO: 41600 events read in total (3666ms).
[08:40:19.479] <TB1> INFO: Test took 4705ms.
[08:40:19.485] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:40:19.793] <TB1> INFO: PixTestAlive::aliveTest() done
[08:40:19.793] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
[08:40:19.795] <TB1> INFO: ----------------------------------------------------------------------
[08:40:19.795] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:40:19.795] <TB1> INFO: ----------------------------------------------------------------------
[08:40:20.114] <TB1> INFO: Expecting 41600 events.
[08:40:23.276] <TB1> INFO: 41600 events read in total (2445ms).
[08:40:23.276] <TB1> INFO: Test took 3479ms.
[08:40:23.277] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:40:23.277] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[08:40:23.605] <TB1> INFO: PixTestAlive::maskTest() done
[08:40:23.605] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:40:23.607] <TB1> INFO: ----------------------------------------------------------------------
[08:40:23.607] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:40:23.607] <TB1> INFO: ----------------------------------------------------------------------
[08:40:23.949] <TB1> INFO: Expecting 41600 events.
[08:40:28.403] <TB1> INFO: 41600 events read in total (3737ms).
[08:40:28.404] <TB1> INFO: Test took 4794ms.
[08:40:28.410] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:40:28.711] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[08:40:28.711] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:40:28.712] <TB1> INFO: PixTestAlive::doTest() done, duration: 13 seconds
[08:40:28.727] <TB1> INFO: ######################################################################
[08:40:28.727] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[08:40:28.727] <TB1> INFO: ######################################################################
[08:40:28.732] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[08:40:28.771] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:40:28.771] <TB1> INFO: run 1 of 1
[08:40:29.087] <TB1> INFO: Expecting 3120000 events.
[08:41:04.873] <TB1> INFO: 851065 events read in total (35069ms).
[08:41:39.696] <TB1> INFO: 1693740 events read in total (69893ms).
[08:42:14.755] <TB1> INFO: 2546065 events read in total (104952ms).
[08:42:37.495] <TB1> INFO: 3120000 events read in total (127691ms).
[08:42:37.540] <TB1> INFO: Test took 128769ms.
[08:42:37.638] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:43:02.111] <TB1> INFO: PixTestBBMap::doTest() done, duration: 153 seconds
[08:43:02.111] <TB1> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
[08:43:02.111] <TB1> INFO: separation cut (per ROC): 93 78 95 80 79 85 73 72 67 70 81 80 69 74 77 81
[08:43:02.182] <TB1> INFO: ######################################################################
[08:43:02.182] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:43:02.182] <TB1> INFO: ######################################################################
[08:43:02.182] <TB1> INFO: ----------------------------------------------------------------------
[08:43:02.182] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:43:02.182] <TB1> INFO: ----------------------------------------------------------------------
[08:43:02.182] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[08:43:02.191] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[08:43:02.191] <TB1> INFO: run 1 of 1
[08:43:02.496] <TB1> INFO: Expecting 31200000 events.
[08:43:26.006] <TB1> INFO: 919750 events read in total (22794ms).
[08:43:50.336] <TB1> INFO: 1824950 events read in total (47124ms).
[08:44:14.738] <TB1> INFO: 2727500 events read in total (71526ms).
[08:44:39.009] <TB1> INFO: 3629950 events read in total (95797ms).
[08:45:03.302] <TB1> INFO: 4531650 events read in total (120090ms).
[08:45:27.645] <TB1> INFO: 5435000 events read in total (144433ms).
[08:45:51.905] <TB1> INFO: 6335300 events read in total (168693ms).
[08:46:16.231] <TB1> INFO: 7237450 events read in total (193019ms).
[08:46:40.473] <TB1> INFO: 8136550 events read in total (217261ms).
[08:47:04.627] <TB1> INFO: 9036600 events read in total (241415ms).
[08:47:29.119] <TB1> INFO: 9935700 events read in total (265907ms).
[08:47:53.547] <TB1> INFO: 10836450 events read in total (290335ms).
[08:48:17.980] <TB1> INFO: 11734650 events read in total (314768ms).
[08:48:42.280] <TB1> INFO: 12634100 events read in total (339068ms).
[08:49:06.687] <TB1> INFO: 13529950 events read in total (363475ms).
[08:49:30.909] <TB1> INFO: 14428600 events read in total (387697ms).
[08:49:55.215] <TB1> INFO: 15322300 events read in total (412003ms).
[08:50:19.503] <TB1> INFO: 16213750 events read in total (436291ms).
[08:50:43.815] <TB1> INFO: 17103150 events read in total (460603ms).
[08:51:08.284] <TB1> INFO: 17990850 events read in total (485072ms).
[08:51:32.588] <TB1> INFO: 18878200 events read in total (509376ms).
[08:51:56.789] <TB1> INFO: 19763850 events read in total (533577ms).
[08:52:21.075] <TB1> INFO: 20651650 events read in total (557863ms).
[08:52:45.351] <TB1> INFO: 21537300 events read in total (582139ms).
[08:53:09.454] <TB1> INFO: 22424000 events read in total (606242ms).
[08:53:33.489] <TB1> INFO: 23307200 events read in total (630277ms).
[08:53:57.457] <TB1> INFO: 24193500 events read in total (654245ms).
[08:54:21.472] <TB1> INFO: 25076950 events read in total (678260ms).
[08:54:45.398] <TB1> INFO: 25962550 events read in total (702186ms).
[08:55:09.548] <TB1> INFO: 26843700 events read in total (726336ms).
[08:55:33.593] <TB1> INFO: 27731300 events read in total (750381ms).
[08:55:57.531] <TB1> INFO: 28616300 events read in total (774319ms).
[08:56:21.572] <TB1> INFO: 29502100 events read in total (798360ms).
[08:56:45.695] <TB1> INFO: 30389300 events read in total (822483ms).
[08:57:07.284] <TB1> INFO: 31200000 events read in total (844072ms).
[08:57:07.319] <TB1> INFO: Test took 845128ms.
[08:57:07.407] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[08:57:07.521] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:08.975] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:10.518] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:12.104] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:13.547] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:15.067] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:16.515] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:18.064] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:19.611] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:21.203] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:22.648] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:24.068] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:25.452] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:26.884] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:28.277] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:29.698] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[08:57:31.335] <TB1> INFO: PixTestScurves::scurves() done
[08:57:31.335] <TB1> INFO: Vcal mean: 92.65 80.37 85.98 89.60 79.30 81.86 74.84 79.71 68.89 79.37 79.86 84.98 67.05 82.43 83.55 80.40
[08:57:31.335] <TB1> INFO: Vcal RMS: 6.15 5.41 5.37 5.34 4.25 4.53 4.67 4.88 4.62 4.76 4.23 5.08 5.35 4.77 4.78 4.27
[08:57:31.335] <TB1> INFO: PixTestScurves::fullTest() done, duration: 869 seconds
[08:57:31.411] <TB1> INFO: ######################################################################
[08:57:31.411] <TB1> INFO: PixTestTrim::doTest()
[08:57:31.411] <TB1> INFO: ######################################################################
[08:57:31.413] <TB1> INFO: ----------------------------------------------------------------------
[08:57:31.413] <TB1> INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[08:57:31.413] <TB1> INFO: ----------------------------------------------------------------------
[08:57:31.493] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[08:57:31.493] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[08:57:31.502] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[08:57:31.502] <TB1> INFO: run 1 of 1
[08:57:31.810] <TB1> INFO: Expecting 13312000 events.
[08:58:00.149] <TB1> INFO: 1067860 events read in total (27612ms).
[08:58:25.234] <TB1> INFO: 2130500 events read in total (52697ms).
[08:58:52.317] <TB1> INFO: 3192040 events read in total (79780ms).
[08:59:19.979] <TB1> INFO: 4252100 events read in total (107442ms).
[08:59:47.721] <TB1> INFO: 5308780 events read in total (135184ms).
[09:00:15.144] <TB1> INFO: 6360520 events read in total (162607ms).
[09:00:42.613] <TB1> INFO: 7415920 events read in total (190076ms).
[09:01:10.175] <TB1> INFO: 8475560 events read in total (217638ms).
[09:01:37.862] <TB1> INFO: 9536160 events read in total (245325ms).
[09:02:05.594] <TB1> INFO: 10600560 events read in total (273057ms).
[09:02:33.237] <TB1> INFO: 11664960 events read in total (300700ms).
[09:03:00.910] <TB1> INFO: 12730680 events read in total (328373ms).
[09:03:16.087] <TB1> INFO: 13312000 events read in total (343550ms).
[09:03:16.122] <TB1> INFO: Test took 344620ms.
[09:03:16.176] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:03:35.259] <TB1> INFO: ROC 0 VthrComp = 97
[09:03:35.259] <TB1> INFO: ROC 1 VthrComp = 82
[09:03:35.259] <TB1> INFO: ROC 2 VthrComp = 95
[09:03:35.259] <TB1> INFO: ROC 3 VthrComp = 94
[09:03:35.259] <TB1> INFO: ROC 4 VthrComp = 83
[09:03:35.259] <TB1> INFO: ROC 5 VthrComp = 89
[09:03:35.259] <TB1> INFO: ROC 6 VthrComp = 80
[09:03:35.260] <TB1> INFO: ROC 7 VthrComp = 84
[09:03:35.260] <TB1> INFO: ROC 8 VthrComp = 74
[09:03:35.260] <TB1> INFO: ROC 9 VthrComp = 82
[09:03:35.260] <TB1> INFO: ROC 10 VthrComp = 87
[09:03:35.260] <TB1> INFO: ROC 11 VthrComp = 87
[09:03:35.260] <TB1> INFO: ROC 12 VthrComp = 73
[09:03:35.260] <TB1> INFO: ROC 13 VthrComp = 87
[09:03:35.260] <TB1> INFO: ROC 14 VthrComp = 86
[09:03:35.261] <TB1> INFO: ROC 15 VthrComp = 87
[09:03:35.261] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[09:03:35.261] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[09:03:35.270] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:03:35.270] <TB1> INFO: run 1 of 1
[09:03:35.578] <TB1> INFO: Expecting 13312000 events.
[09:04:01.358] <TB1> INFO: 780500 events read in total (25063ms).
[09:04:26.350] <TB1> INFO: 1557620 events read in total (50055ms).
[09:04:49.072] <TB1> INFO: 2334680 events read in total (72777ms).
[09:05:12.044] <TB1> INFO: 3111760 events read in total (95749ms).
[09:05:34.824] <TB1> INFO: 3887420 events read in total (118529ms).
[09:05:57.730] <TB1> INFO: 4664340 events read in total (141435ms).
[09:06:20.538] <TB1> INFO: 5440720 events read in total (164243ms).
[09:06:44.015] <TB1> INFO: 6216780 events read in total (187720ms).
[09:07:09.044] <TB1> INFO: 6990040 events read in total (212749ms).
[09:07:33.887] <TB1> INFO: 7760000 events read in total (237592ms).
[09:07:58.781] <TB1> INFO: 8527940 events read in total (262486ms).
[09:08:23.702] <TB1> INFO: 9295700 events read in total (287407ms).
[09:08:48.476] <TB1> INFO: 10062140 events read in total (312181ms).
[09:09:13.272] <TB1> INFO: 10827880 events read in total (336977ms).
[09:09:38.044] <TB1> INFO: 11593100 events read in total (361749ms).
[09:10:02.856] <TB1> INFO: 12358860 events read in total (386561ms).
[09:10:27.641] <TB1> INFO: 13125960 events read in total (411346ms).
[09:10:33.988] <TB1> INFO: 13312000 events read in total (417693ms).
[09:10:34.030] <TB1> INFO: Test took 418760ms.
[09:10:34.168] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:10:57.787] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 61.3831 for pixel 14/79 mean/min/max = 46.2992/31.1122/61.4862
[09:10:57.787] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 62.172 for pixel 11/1 mean/min/max = 47.0328/31.8234/62.2422
[09:10:57.788] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 58.195 for pixel 51/67 mean/min/max = 45.2385/32.1954/58.2816
[09:10:57.788] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 58.0349 for pixel 6/1 mean/min/max = 45.0051/31.8842/58.126
[09:10:57.788] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 57.8981 for pixel 1/79 mean/min/max = 45.3822/32.8096/57.9547
[09:10:57.788] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 56.9516 for pixel 51/66 mean/min/max = 45.045/32.9317/57.1583
[09:10:57.789] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 58.0688 for pixel 11/0 mean/min/max = 45.3393/32.5533/58.1254
[09:10:57.789] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 58.9586 for pixel 21/4 mean/min/max = 45.7191/32.1706/59.2675
[09:10:57.789] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 56.0349 for pixel 51/0 mean/min/max = 45.0772/34.0868/56.0675
[09:10:57.789] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 59.5608 for pixel 0/2 mean/min/max = 45.605/31.6231/59.5869
[09:10:57.790] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 56.4658 for pixel 0/65 mean/min/max = 44.4423/32.1716/56.713
[09:10:57.790] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 59.3325 for pixel 5/9 mean/min/max = 45.9746/32.4129/59.5364
[09:10:57.790] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 59.4498 for pixel 11/10 mean/min/max = 46.5593/33.6297/59.4888
[09:10:57.790] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 58.5642 for pixel 14/8 mean/min/max = 45.3011/32.0341/58.5681
[09:10:57.791] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 58.932 for pixel 0/23 mean/min/max = 45.6959/32.4577/58.9341
[09:10:57.791] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 56.5754 for pixel 31/79 mean/min/max = 44.3483/31.8545/56.8421
[09:10:57.791] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:10:57.924] <TB1> INFO: Expecting 1029120 events.
[09:11:21.886] <TB1> INFO: 1029120 events read in total (23241ms).
[09:11:21.892] <TB1> INFO: Expecting 1029120 events.
[09:11:45.635] <TB1> INFO: 1029120 events read in total (23212ms).
[09:11:45.642] <TB1> INFO: Expecting 1029120 events.
[09:12:09.554] <TB1> INFO: 1029120 events read in total (23372ms).
[09:12:09.565] <TB1> INFO: Expecting 1029120 events.
[09:12:33.388] <TB1> INFO: 1029120 events read in total (23294ms).
[09:12:33.401] <TB1> INFO: Expecting 1029120 events.
[09:12:54.918] <TB1> INFO: 1029120 events read in total (20976ms).
[09:12:54.930] <TB1> INFO: Expecting 1029120 events.
[09:13:18.335] <TB1> INFO: 1029120 events read in total (22849ms).
[09:13:18.351] <TB1> INFO: Expecting 1029120 events.
[09:13:42.320] <TB1> INFO: 1029120 events read in total (23429ms).
[09:13:42.339] <TB1> INFO: Expecting 1029120 events.
[09:14:06.028] <TB1> INFO: 1029120 events read in total (23160ms).
[09:14:06.048] <TB1> INFO: Expecting 1029120 events.
[09:14:29.856] <TB1> INFO: 1029120 events read in total (23280ms).
[09:14:29.878] <TB1> INFO: Expecting 1029120 events.
[09:14:53.647] <TB1> INFO: 1029120 events read in total (23236ms).
[09:14:53.669] <TB1> INFO: Expecting 1029120 events.
[09:15:17.526] <TB1> INFO: 1029120 events read in total (23324ms).
[09:15:17.549] <TB1> INFO: Expecting 1029120 events.
[09:15:41.484] <TB1> INFO: 1029120 events read in total (23407ms).
[09:15:41.510] <TB1> INFO: Expecting 1029120 events.
[09:16:05.547] <TB1> INFO: 1029120 events read in total (23509ms).
[09:16:05.575] <TB1> INFO: Expecting 1029120 events.
[09:16:29.614] <TB1> INFO: 1029120 events read in total (23511ms).
[09:16:29.648] <TB1> INFO: Expecting 1029120 events.
[09:16:53.383] <TB1> INFO: 1029120 events read in total (23207ms).
[09:16:53.414] <TB1> INFO: Expecting 1029120 events.
[09:17:17.260] <TB1> INFO: 1029120 events read in total (23318ms).
[09:17:17.294] <TB1> INFO: Test took 379503ms.
[09:17:18.317] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[09:17:18.325] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:17:18.326] <TB1> INFO: run 1 of 1
[09:17:18.637] <TB1> INFO: Expecting 16640000 events.
[09:17:43.796] <TB1> INFO: 726040 events read in total (24442ms).
[09:18:08.047] <TB1> INFO: 1449160 events read in total (48693ms).
[09:18:32.567] <TB1> INFO: 2171780 events read in total (73213ms).
[09:18:57.008] <TB1> INFO: 2895280 events read in total (97654ms).
[09:19:21.457] <TB1> INFO: 3618480 events read in total (122103ms).
[09:19:46.010] <TB1> INFO: 4341100 events read in total (146656ms).
[09:20:10.646] <TB1> INFO: 5062960 events read in total (171292ms).
[09:20:35.169] <TB1> INFO: 5786380 events read in total (195815ms).
[09:20:59.733] <TB1> INFO: 6509380 events read in total (220379ms).
[09:21:24.181] <TB1> INFO: 7231640 events read in total (244827ms).
[09:21:48.635] <TB1> INFO: 7954160 events read in total (269281ms).
[09:22:13.056] <TB1> INFO: 8674460 events read in total (293702ms).
[09:22:37.377] <TB1> INFO: 9391980 events read in total (318023ms).
[09:23:01.872] <TB1> INFO: 10109080 events read in total (342518ms).
[09:23:26.401] <TB1> INFO: 10824900 events read in total (367047ms).
[09:23:50.903] <TB1> INFO: 11540560 events read in total (391549ms).
[09:24:15.428] <TB1> INFO: 12255720 events read in total (416074ms).
[09:24:39.774] <TB1> INFO: 12970280 events read in total (440420ms).
[09:25:04.134] <TB1> INFO: 13684340 events read in total (464780ms).
[09:25:28.530] <TB1> INFO: 14398180 events read in total (489176ms).
[09:25:52.955] <TB1> INFO: 15112580 events read in total (513601ms).
[09:26:17.416] <TB1> INFO: 15826440 events read in total (538062ms).
[09:26:41.928] <TB1> INFO: 16542220 events read in total (562574ms).
[09:26:45.661] <TB1> INFO: 16640000 events read in total (566307ms).
[09:26:45.730] <TB1> INFO: Test took 567404ms.
[09:26:45.953] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:27:11.600] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 1.003682 .. 50.792896
[09:27:11.675] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 1 .. 60 (-1/-1) hits flags = 16 (plus default)
[09:27:11.683] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:27:11.683] <TB1> INFO: run 1 of 1
[09:27:11.989] <TB1> INFO: Expecting 4992000 events.
[09:27:39.215] <TB1> INFO: 923800 events read in total (26504ms).
[09:28:05.768] <TB1> INFO: 1848760 events read in total (53057ms).
[09:28:32.311] <TB1> INFO: 2773940 events read in total (79600ms).
[09:28:58.748] <TB1> INFO: 3693980 events read in total (106037ms).
[09:29:25.219] <TB1> INFO: 4608120 events read in total (132508ms).
[09:29:36.573] <TB1> INFO: 4992000 events read in total (143862ms).
[09:29:36.587] <TB1> INFO: Test took 144904ms.
[09:29:36.625] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:29:50.877] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 16.738672 .. 45.659665
[09:29:50.956] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 6 .. 55 (-1/-1) hits flags = 16 (plus default)
[09:29:50.965] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:29:50.965] <TB1> INFO: run 1 of 1
[09:29:51.281] <TB1> INFO: Expecting 4160000 events.
[09:30:18.607] <TB1> INFO: 933380 events read in total (26608ms).
[09:30:45.271] <TB1> INFO: 1866640 events read in total (53272ms).
[09:31:09.624] <TB1> INFO: 2798960 events read in total (77625ms).
[09:31:35.349] <TB1> INFO: 3728860 events read in total (103350ms).
[09:31:48.011] <TB1> INFO: 4160000 events read in total (116012ms).
[09:31:48.026] <TB1> INFO: Test took 117061ms.
[09:31:48.057] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:32:01.808] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 21.530902 .. 42.744120
[09:32:01.887] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 11 .. 52 (-1/-1) hits flags = 16 (plus default)
[09:32:01.896] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:32:01.896] <TB1> INFO: run 1 of 1
[09:32:02.210] <TB1> INFO: Expecting 3494400 events.
[09:32:29.575] <TB1> INFO: 930440 events read in total (26648ms).
[09:32:56.205] <TB1> INFO: 1861120 events read in total (53278ms).
[09:33:22.817] <TB1> INFO: 2789780 events read in total (79891ms).
[09:33:43.147] <TB1> INFO: 3494400 events read in total (100220ms).
[09:33:43.165] <TB1> INFO: Test took 101269ms.
[09:33:43.195] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:33:56.439] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 22.940591 .. 42.744120
[09:33:56.521] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 12 .. 52 (-1/-1) hits flags = 16 (plus default)
[09:33:56.530] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:33:56.530] <TB1> INFO: run 1 of 1
[09:33:56.845] <TB1> INFO: Expecting 3411200 events.
[09:34:21.888] <TB1> INFO: 923800 events read in total (24325ms).
[09:34:48.585] <TB1> INFO: 1847380 events read in total (51022ms).
[09:35:14.176] <TB1> INFO: 2770100 events read in total (76614ms).
[09:35:31.255] <TB1> INFO: 3411200 events read in total (93692ms).
[09:35:31.271] <TB1> INFO: Test took 94742ms.
[09:35:31.304] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:35:44.629] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[09:35:44.629] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[09:35:44.639] <TB1> INFO: dacScan split into 1 runs with ntrig = 20
[09:35:44.639] <TB1> INFO: run 1 of 1
[09:35:44.956] <TB1> INFO: Expecting 3411200 events.
[09:36:09.936] <TB1> INFO: 879700 events read in total (24263ms).
[09:36:33.931] <TB1> INFO: 1759480 events read in total (48258ms).
[09:36:59.655] <TB1> INFO: 2638660 events read in total (73983ms).
[09:37:22.646] <TB1> INFO: 3411200 events read in total (96973ms).
[09:37:22.657] <TB1> INFO: Test took 98018ms.
[09:37:22.687] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:37:35.804] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C0.dat
[09:37:35.804] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C1.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C2.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C3.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C4.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C5.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C6.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C7.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C8.dat
[09:37:35.805] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C9.dat
[09:37:35.806] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C10.dat
[09:37:35.806] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C11.dat
[09:37:35.806] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C12.dat
[09:37:35.806] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C13.dat
[09:37:35.806] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C14.dat
[09:37:35.806] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C15.dat
[09:37:35.806] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C0.dat
[09:37:35.812] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C1.dat
[09:37:35.818] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C2.dat
[09:37:35.825] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C3.dat
[09:37:35.832] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C4.dat
[09:37:35.838] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C5.dat
[09:37:35.844] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C6.dat
[09:37:35.851] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C7.dat
[09:37:35.857] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C8.dat
[09:37:35.864] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C9.dat
[09:37:35.870] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C10.dat
[09:37:35.876] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C11.dat
[09:37:35.882] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C12.dat
[09:37:35.888] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C13.dat
[09:37:35.895] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C14.dat
[09:37:35.901] <TB1> INFO: write trim parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//trimParameters35_C15.dat
[09:37:35.908] <TB1> INFO: PixTestTrim::trimTest() done
[09:37:35.908] <TB1> INFO: vtrim: 104 110 91 92 80 83 95 92 84 94 86 98 98 98 86 87
[09:37:35.908] <TB1> INFO: vthrcomp: 97 82 95 94 83 89 80 84 74 82 87 87 73 87 86 87
[09:37:35.908] <TB1> INFO: vcal mean: 34.96 35.01 35.01 34.97 35.01 35.01 34.99 35.00 34.97 34.95 35.01 34.97 34.99 34.99 34.99 34.96
[09:37:35.908] <TB1> INFO: vcal RMS: 0.72 0.76 0.67 0.77 0.68 0.63 0.64 0.68 0.82 0.70 0.65 0.72 0.69 0.72 0.71 0.68
[09:37:35.908] <TB1> INFO: bits mean: 9.18 9.23 8.53 9.35 8.88 8.60 9.06 9.12 8.90 9.00 9.13 9.26 8.68 9.53 8.84 9.34
[09:37:35.908] <TB1> INFO: bits RMS: 2.90 2.75 3.08 2.85 2.90 2.98 2.84 2.81 2.66 2.98 2.95 2.69 2.70 2.74 2.92 2.88
[09:37:35.918] <TB1> INFO: ----------------------------------------------------------------------
[09:37:35.918] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[09:37:35.918] <TB1> INFO: ----------------------------------------------------------------------
[09:37:35.922] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[09:37:35.932] <TB1> INFO: dacScan split into 1 runs with ntrig = 10
[09:37:35.932] <TB1> INFO: run 1 of 1
[09:37:36.246] <TB1> INFO: Expecting 8320000 events.
[09:38:06.095] <TB1> INFO: 900450 events read in total (29132ms).
[09:38:33.057] <TB1> INFO: 1795790 events read in total (56094ms).
[09:39:02.280] <TB1> INFO: 2688580 events read in total (85317ms).
[09:39:31.573] <TB1> INFO: 3579620 events read in total (114610ms).
[09:40:00.773] <TB1> INFO: 4465900 events read in total (143810ms).
[09:40:28.073] <TB1> INFO: 5347530 events read in total (171110ms).
[09:40:57.118] <TB1> INFO: 6227840 events read in total (200155ms).
[09:41:23.577] <TB1> INFO: 7107750 events read in total (226614ms).
[09:41:52.612] <TB1> INFO: 7989570 events read in total (255649ms).
[09:42:03.683] <TB1> INFO: 8320000 events read in total (266720ms).
[09:42:03.719] <TB1> INFO: Test took 267788ms.
[09:42:03.842] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:42:30.447] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[09:42:30.456] <TB1> INFO: dacScan split into 1 runs with ntrig = 10
[09:42:30.456] <TB1> INFO: run 1 of 1
[09:42:30.770] <TB1> INFO: Expecting 6656000 events.
[09:43:01.402] <TB1> INFO: 945480 events read in total (29915ms).
[09:43:31.218] <TB1> INFO: 1884240 events read in total (59731ms).
[09:44:00.896] <TB1> INFO: 2819640 events read in total (89409ms).
[09:44:29.144] <TB1> INFO: 3747230 events read in total (117657ms).
[09:44:56.797] <TB1> INFO: 4669460 events read in total (145310ms).
[09:45:26.367] <TB1> INFO: 5589820 events read in total (174880ms).
[09:45:53.592] <TB1> INFO: 6512580 events read in total (202105ms).
[09:45:58.513] <TB1> INFO: 6656000 events read in total (207026ms).
[09:45:58.547] <TB1> INFO: Test took 208091ms.
[09:45:58.636] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:46:22.770] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 150 (-1/-1) hits flags = 16 (plus default)
[09:46:22.779] <TB1> INFO: dacScan split into 1 runs with ntrig = 10
[09:46:22.779] <TB1> INFO: run 1 of 1
[09:46:23.107] <TB1> INFO: Expecting 6281600 events.
[09:46:53.788] <TB1> INFO: 969490 events read in total (29964ms).
[09:47:22.667] <TB1> INFO: 1931100 events read in total (58843ms).
[09:47:51.182] <TB1> INFO: 2888410 events read in total (87359ms).
[09:48:21.217] <TB1> INFO: 3835120 events read in total (117393ms).
[09:48:51.170] <TB1> INFO: 4777880 events read in total (147346ms).
[09:49:21.107] <TB1> INFO: 5720700 events read in total (177283ms).
[09:49:37.592] <TB1> INFO: 6281600 events read in total (193768ms).
[09:49:37.619] <TB1> INFO: Test took 194840ms.
[09:49:37.691] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:50:00.683] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[09:50:00.693] <TB1> INFO: dacScan split into 1 runs with ntrig = 10
[09:50:00.693] <TB1> INFO: run 1 of 1
[09:50:01.010] <TB1> INFO: Expecting 6240000 events.
[09:50:31.981] <TB1> INFO: 971750 events read in total (30254ms).
[09:51:02.153] <TB1> INFO: 1935480 events read in total (60426ms).
[09:51:32.149] <TB1> INFO: 2894850 events read in total (90423ms).
[09:51:59.821] <TB1> INFO: 3843510 events read in total (118094ms).
[09:52:29.829] <TB1> INFO: 4788110 events read in total (148102ms).
[09:52:59.597] <TB1> INFO: 5732620 events read in total (177870ms).
[09:53:15.762] <TB1> INFO: 6240000 events read in total (194035ms).
[09:53:15.791] <TB1> INFO: Test took 195098ms.
[09:53:15.863] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:53:38.129] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 148 (-1/-1) hits flags = 16 (plus default)
[09:53:38.138] <TB1> INFO: dacScan split into 1 runs with ntrig = 10
[09:53:38.138] <TB1> INFO: run 1 of 1
[09:53:38.447] <TB1> INFO: Expecting 6198400 events.
[09:54:08.448] <TB1> INFO: 973900 events read in total (29278ms).
[09:54:36.060] <TB1> INFO: 1939580 events read in total (56890ms).
[09:55:06.242] <TB1> INFO: 2900980 events read in total (87073ms).
[09:55:35.553] <TB1> INFO: 3851360 events read in total (116383ms).
[09:56:04.660] <TB1> INFO: 4798130 events read in total (145490ms).
[09:56:34.655] <TB1> INFO: 5744890 events read in total (175485ms).
[09:56:49.131] <TB1> INFO: 6198400 events read in total (189961ms).
[09:56:49.159] <TB1> INFO: Test took 191021ms.
[09:56:49.231] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:13.308] <TB1> INFO: PixTestTrim::trimBitTest() done
[09:57:13.311] <TB1> INFO: PixTestTrim::doTest() done, duration: 3581 seconds
[09:57:14.041] <TB1> INFO: ######################################################################
[09:57:14.041] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[09:57:14.041] <TB1> INFO: ######################################################################
[09:57:14.358] <TB1> INFO: Expecting 41600 events.
[09:57:18.813] <TB1> INFO: 41600 events read in total (3733ms).
[09:57:18.814] <TB1> INFO: Test took 4770ms.
[09:57:18.820] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:19.396] <TB1> INFO: Expecting 41600 events.
[09:57:23.872] <TB1> INFO: 41600 events read in total (3759ms).
[09:57:23.872] <TB1> INFO: Test took 4793ms.
[09:57:23.879] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:24.226] <TB1> INFO: Expecting 41600 events.
[09:57:28.714] <TB1> INFO: 41600 events read in total (3771ms).
[09:57:28.715] <TB1> INFO: Test took 4814ms.
[09:57:28.722] <TB1> INFO: Fetched DAQ statistics. Counters are being reset now.
[09:57:28.730] <TB1> INFO: The DUT currently contains the following objects:
[09:57:28.730] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:28.730] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:28.730] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:28.730] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:28.730] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:28.730] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:29.063] <TB1> INFO: Expecting 2560 events.
[09:57:30.136] <TB1> INFO: 2560 events read in total (356ms).
[09:57:30.136] <TB1> INFO: Test took 1406ms.
[09:57:30.137] <TB1> INFO: The DUT currently contains the following objects:
[09:57:30.137] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:30.137] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:30.137] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:30.137] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:30.137] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.137] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.137] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.137] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.137] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.137] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.138] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:30.552] <TB1> INFO: Expecting 2560 events.
[09:57:31.623] <TB1> INFO: 2560 events read in total (354ms).
[09:57:31.623] <TB1> INFO: Test took 1485ms.
[09:57:31.624] <TB1> INFO: The DUT currently contains the following objects:
[09:57:31.624] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:31.624] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:31.624] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:31.624] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:31.624] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.624] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.624] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.624] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:31.625] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:32.039] <TB1> INFO: Expecting 2560 events.
[09:57:33.111] <TB1> INFO: 2560 events read in total (355ms).
[09:57:33.112] <TB1> INFO: Test took 1487ms.
[09:57:33.112] <TB1> INFO: The DUT currently contains the following objects:
[09:57:33.112] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:33.112] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:33.112] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:33.113] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:33.113] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.113] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:33.528] <TB1> INFO: Expecting 2560 events.
[09:57:34.592] <TB1> INFO: 2560 events read in total (347ms).
[09:57:34.592] <TB1> INFO: Test took 1478ms.
[09:57:34.592] <TB1> INFO: The DUT currently contains the following objects:
[09:57:34.592] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:34.592] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:34.592] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:34.593] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:34.593] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:34.593] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:35.009] <TB1> INFO: Expecting 2560 events.
[09:57:36.082] <TB1> INFO: 2560 events read in total (356ms).
[09:57:36.082] <TB1> INFO: Test took 1489ms.
[09:57:36.082] <TB1> INFO: The DUT currently contains the following objects:
[09:57:36.083] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:36.083] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:36.083] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:36.083] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:36.083] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.083] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:36.498] <TB1> INFO: Expecting 2560 events.
[09:57:37.569] <TB1> INFO: 2560 events read in total (354ms).
[09:57:37.569] <TB1> INFO: Test took 1486ms.
[09:57:37.570] <TB1> INFO: The DUT currently contains the following objects:
[09:57:37.570] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:37.570] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:37.570] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:37.570] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:37.570] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.570] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:37.985] <TB1> INFO: Expecting 2560 events.
[09:57:39.058] <TB1> INFO: 2560 events read in total (356ms).
[09:57:39.058] <TB1> INFO: Test took 1488ms.
[09:57:39.058] <TB1> INFO: The DUT currently contains the following objects:
[09:57:39.058] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:39.058] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:39.059] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:39.059] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:39.059] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.059] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:39.474] <TB1> INFO: Expecting 2560 events.
[09:57:40.544] <TB1> INFO: 2560 events read in total (353ms).
[09:57:40.544] <TB1> INFO: Test took 1485ms.
[09:57:40.545] <TB1> INFO: The DUT currently contains the following objects:
[09:57:40.545] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:40.545] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:40.545] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:40.545] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:40.545] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.545] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:40.960] <TB1> INFO: Expecting 2560 events.
[09:57:42.031] <TB1> INFO: 2560 events read in total (354ms).
[09:57:42.032] <TB1> INFO: Test took 1487ms.
[09:57:42.032] <TB1> INFO: The DUT currently contains the following objects:
[09:57:42.032] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:42.032] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:42.032] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:42.032] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:42.032] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.032] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.032] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.033] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:42.447] <TB1> INFO: Expecting 2560 events.
[09:57:43.519] <TB1> INFO: 2560 events read in total (355ms).
[09:57:43.519] <TB1> INFO: Test took 1486ms.
[09:57:43.520] <TB1> INFO: The DUT currently contains the following objects:
[09:57:43.520] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:43.520] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:43.520] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:43.520] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:43.520] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.520] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.521] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.521] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.521] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:43.935] <TB1> INFO: Expecting 2560 events.
[09:57:45.006] <TB1> INFO: 2560 events read in total (354ms).
[09:57:45.006] <TB1> INFO: Test took 1485ms.
[09:57:45.010] <TB1> INFO: The DUT currently contains the following objects:
[09:57:45.010] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:45.010] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:45.010] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:45.010] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:45.010] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.010] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.011] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:45.421] <TB1> INFO: Expecting 2560 events.
[09:57:46.493] <TB1> INFO: 2560 events read in total (356ms).
[09:57:46.494] <TB1> INFO: Test took 1483ms.
[09:57:46.494] <TB1> INFO: The DUT currently contains the following objects:
[09:57:46.494] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:46.494] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:46.494] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:46.494] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:46.494] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.494] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.494] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.495] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:46.910] <TB1> INFO: Expecting 2560 events.
[09:57:47.982] <TB1> INFO: 2560 events read in total (355ms).
[09:57:47.982] <TB1> INFO: Test took 1487ms.
[09:57:47.983] <TB1> INFO: The DUT currently contains the following objects:
[09:57:47.983] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:47.983] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:47.983] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:47.983] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:47.983] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.983] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.984] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:47.984] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:48.398] <TB1> INFO: Expecting 2560 events.
[09:57:49.470] <TB1> INFO: 2560 events read in total (355ms).
[09:57:49.470] <TB1> INFO: Test took 1486ms.
[09:57:49.471] <TB1> INFO: The DUT currently contains the following objects:
[09:57:49.471] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:49.471] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:49.471] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:49.471] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:49.471] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.471] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.471] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.471] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.471] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.471] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.471] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.472] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:49.886] <TB1> INFO: Expecting 2560 events.
[09:57:50.958] <TB1> INFO: 2560 events read in total (355ms).
[09:57:50.958] <TB1> INFO: Test took 1486ms.
[09:57:50.958] <TB1> INFO: The DUT currently contains the following objects:
[09:57:50.958] <TB1> INFO: 2 TBM Cores tbm09c (2 ON)
[09:57:50.959] <TB1> INFO: TBM Core alpha (0): 7 registers set
[09:57:50.959] <TB1> INFO: TBM Core beta (1): 7 registers set
[09:57:50.959] <TB1> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[09:57:50.959] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:50.959] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[09:57:51.374] <TB1> INFO: Expecting 2560 events.
[09:57:52.446] <TB1> INFO: 2560 events read in total (355ms).
[09:57:52.446] <TB1> INFO: Test took 1487ms.
[09:57:52.451] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:57:52.863] <TB1> INFO: Expecting 655360 events.
[09:58:08.212] <TB1> INFO: 655360 events read in total (14632ms).
[09:58:08.222] <TB1> INFO: Expecting 655360 events.
[09:58:23.251] <TB1> INFO: 655360 events read in total (14501ms).
[09:58:23.264] <TB1> INFO: Expecting 655360 events.
[09:58:39.325] <TB1> INFO: 655360 events read in total (15533ms).
[09:58:39.341] <TB1> INFO: Expecting 655360 events.
[09:58:54.309] <TB1> INFO: 655360 events read in total (14440ms).
[09:58:54.328] <TB1> INFO: Expecting 655360 events.
[09:59:10.594] <TB1> INFO: 655360 events read in total (15738ms).
[09:59:10.617] <TB1> INFO: Expecting 655360 events.
[09:59:27.310] <TB1> INFO: 655360 events read in total (16165ms).
[09:59:27.339] <TB1> INFO: Expecting 655360 events.
[09:59:42.501] <TB1> INFO: 655360 events read in total (14633ms).
[09:59:42.532] <TB1> INFO: Expecting 655360 events.
[09:59:58.574] <TB1> INFO: 655360 events read in total (15514ms).
[09:59:58.611] <TB1> INFO: Expecting 655360 events.
[10:00:15.147] <TB1> INFO: 655360 events read in total (16008ms).
[10:00:15.187] <TB1> INFO: Expecting 655360 events.
[10:00:31.661] <TB1> INFO: 655360 events read in total (15945ms).
[10:00:31.702] <TB1> INFO: Expecting 655360 events.
[10:00:48.260] <TB1> INFO: 655360 events read in total (16030ms).
[10:00:48.308] <TB1> INFO: Expecting 655360 events.
[10:01:04.763] <TB1> INFO: 655360 events read in total (15927ms).
[10:01:04.810] <TB1> INFO: Expecting 655360 events.
[10:01:21.364] <TB1> INFO: 655360 events read in total (16025ms).
[10:01:21.413] <TB1> INFO: Expecting 655360 events.
[10:01:36.715] <TB1> INFO: 655360 events read in total (14774ms).
[10:01:36.769] <TB1> INFO: Expecting 655360 events.
[10:01:51.769] <TB1> INFO: 655360 events read in total (14472ms).
[10:01:51.827] <TB1> INFO: Expecting 655360 events.
[10:02:08.392] <TB1> INFO: 655360 events read in total (16037ms).
[10:02:08.457] <TB1> INFO: Test took 256006ms.
[10:02:08.548] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:08.852] <TB1> INFO: Expecting 655360 events.
[10:02:25.539] <TB1> INFO: 655360 events read in total (15970ms).
[10:02:25.549] <TB1> INFO: Expecting 655360 events.
[10:02:42.011] <TB1> INFO: 655360 events read in total (15934ms).
[10:02:42.024] <TB1> INFO: Expecting 655360 events.
[10:02:58.562] <TB1> INFO: 655360 events read in total (16010ms).
[10:02:58.579] <TB1> INFO: Expecting 655360 events.
[10:03:15.036] <TB1> INFO: 655360 events read in total (15928ms).
[10:03:15.055] <TB1> INFO: Expecting 655360 events.
[10:03:30.270] <TB1> INFO: 655360 events read in total (14686ms).
[10:03:30.292] <TB1> INFO: Expecting 655360 events.
[10:03:45.601] <TB1> INFO: 655360 events read in total (14781ms).
[10:03:45.629] <TB1> INFO: Expecting 655360 events.
[10:04:01.809] <TB1> INFO: 655360 events read in total (15652ms).
[10:04:01.839] <TB1> INFO: Expecting 655360 events.
[10:04:18.498] <TB1> INFO: 655360 events read in total (16131ms).
[10:04:18.533] <TB1> INFO: Expecting 655360 events.
[10:04:35.051] <TB1> INFO: 655360 events read in total (15990ms).
[10:04:35.090] <TB1> INFO: Expecting 655360 events.
[10:04:51.657] <TB1> INFO: 655360 events read in total (16039ms).
[10:04:51.698] <TB1> INFO: Expecting 655360 events.
[10:05:07.410] <TB1> INFO: 655360 events read in total (15184ms).
[10:05:07.454] <TB1> INFO: Expecting 655360 events.
[10:05:22.661] <TB1> INFO: 655360 events read in total (14679ms).
[10:05:22.709] <TB1> INFO: Expecting 655360 events.
[10:05:37.937] <TB1> INFO: 655360 events read in total (14700ms).
[10:05:37.993] <TB1> INFO: Expecting 655360 events.
[10:05:53.321] <TB1> INFO: 655360 events read in total (14800ms).
[10:05:53.379] <TB1> INFO: Expecting 655360 events.
[10:06:08.725] <TB1> INFO: 655360 events read in total (14818ms).
[10:06:08.785] <TB1> INFO: Expecting 655360 events.
[10:06:24.075] <TB1> INFO: 655360 events read in total (14762ms).
[10:06:24.136] <TB1> INFO: Test took 255589ms.
[10:06:24.355] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.363] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.370] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.379] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.387] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.394] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[10:06:24.402] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.410] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.417] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.426] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.435] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.444] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.453] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.463] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.470] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.480] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.488] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:06:24.547] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C0.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C1.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C2.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C3.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C4.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C5.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C6.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C7.dat
[10:06:24.548] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C8.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C9.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C10.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C11.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C12.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C13.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C14.dat
[10:06:24.549] <TB1> INFO: write dac parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//dacParameters35_C15.dat
[10:06:24.868] <TB1> INFO: Expecting 41600 events.
[10:06:29.224] <TB1> INFO: 41600 events read in total (3639ms).
[10:06:29.225] <TB1> INFO: Test took 4671ms.
[10:06:29.803] <TB1> INFO: Expecting 41600 events.
[10:06:34.138] <TB1> INFO: 41600 events read in total (3618ms).
[10:06:34.139] <TB1> INFO: Test took 4666ms.
[10:06:34.718] <TB1> INFO: Expecting 41600 events.
[10:06:39.180] <TB1> INFO: 41600 events read in total (3746ms).
[10:06:39.181] <TB1> INFO: Test took 4795ms.
[10:06:39.421] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:39.553] <TB1> INFO: Expecting 2560 events.
[10:06:40.640] <TB1> INFO: 2560 events read in total (369ms).
[10:06:40.642] <TB1> INFO: Test took 1222ms.
[10:06:40.645] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:41.057] <TB1> INFO: Expecting 2560 events.
[10:06:42.130] <TB1> INFO: 2560 events read in total (355ms).
[10:06:42.130] <TB1> INFO: Test took 1486ms.
[10:06:42.134] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:42.546] <TB1> INFO: Expecting 2560 events.
[10:06:43.617] <TB1> INFO: 2560 events read in total (353ms).
[10:06:43.617] <TB1> INFO: Test took 1483ms.
[10:06:43.620] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:44.035] <TB1> INFO: Expecting 2560 events.
[10:06:45.106] <TB1> INFO: 2560 events read in total (354ms).
[10:06:45.106] <TB1> INFO: Test took 1486ms.
[10:06:45.109] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:45.523] <TB1> INFO: Expecting 2560 events.
[10:06:46.594] <TB1> INFO: 2560 events read in total (354ms).
[10:06:46.595] <TB1> INFO: Test took 1486ms.
[10:06:46.598] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:47.011] <TB1> INFO: Expecting 2560 events.
[10:06:48.083] <TB1> INFO: 2560 events read in total (354ms).
[10:06:48.084] <TB1> INFO: Test took 1486ms.
[10:06:48.088] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:48.501] <TB1> INFO: Expecting 2560 events.
[10:06:49.572] <TB1> INFO: 2560 events read in total (354ms).
[10:06:49.573] <TB1> INFO: Test took 1485ms.
[10:06:49.579] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:49.990] <TB1> INFO: Expecting 2560 events.
[10:06:51.061] <TB1> INFO: 2560 events read in total (355ms).
[10:06:51.062] <TB1> INFO: Test took 1483ms.
[10:06:51.065] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:51.479] <TB1> INFO: Expecting 2560 events.
[10:06:52.552] <TB1> INFO: 2560 events read in total (357ms).
[10:06:52.552] <TB1> INFO: Test took 1487ms.
[10:06:52.556] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:52.969] <TB1> INFO: Expecting 2560 events.
[10:06:54.042] <TB1> INFO: 2560 events read in total (356ms).
[10:06:54.042] <TB1> INFO: Test took 1486ms.
[10:06:54.046] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:54.459] <TB1> INFO: Expecting 2560 events.
[10:06:55.522] <TB1> INFO: 2560 events read in total (347ms).
[10:06:55.522] <TB1> INFO: Test took 1476ms.
[10:06:55.525] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:55.939] <TB1> INFO: Expecting 2560 events.
[10:06:57.004] <TB1> INFO: 2560 events read in total (348ms).
[10:06:57.005] <TB1> INFO: Test took 1480ms.
[10:06:57.008] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:57.422] <TB1> INFO: Expecting 2560 events.
[10:06:58.493] <TB1> INFO: 2560 events read in total (353ms).
[10:06:58.494] <TB1> INFO: Test took 1486ms.
[10:06:58.497] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:06:58.910] <TB1> INFO: Expecting 2560 events.
[10:06:59.984] <TB1> INFO: 2560 events read in total (356ms).
[10:06:59.984] <TB1> INFO: Test took 1487ms.
[10:06:59.987] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:00.401] <TB1> INFO: Expecting 2560 events.
[10:07:01.473] <TB1> INFO: 2560 events read in total (355ms).
[10:07:01.473] <TB1> INFO: Test took 1486ms.
[10:07:01.477] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:01.890] <TB1> INFO: Expecting 2560 events.
[10:07:02.961] <TB1> INFO: 2560 events read in total (354ms).
[10:07:02.961] <TB1> INFO: Test took 1485ms.
[10:07:02.964] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:03.378] <TB1> INFO: Expecting 2560 events.
[10:07:04.448] <TB1> INFO: 2560 events read in total (353ms).
[10:07:04.449] <TB1> INFO: Test took 1485ms.
[10:07:04.452] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:04.866] <TB1> INFO: Expecting 2560 events.
[10:07:05.938] <TB1> INFO: 2560 events read in total (355ms).
[10:07:05.939] <TB1> INFO: Test took 1487ms.
[10:07:05.942] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:06.355] <TB1> INFO: Expecting 2560 events.
[10:07:07.428] <TB1> INFO: 2560 events read in total (356ms).
[10:07:07.428] <TB1> INFO: Test took 1486ms.
[10:07:07.432] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:07.845] <TB1> INFO: Expecting 2560 events.
[10:07:08.918] <TB1> INFO: 2560 events read in total (356ms).
[10:07:08.918] <TB1> INFO: Test took 1487ms.
[10:07:08.922] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:09.335] <TB1> INFO: Expecting 2560 events.
[10:07:10.407] <TB1> INFO: 2560 events read in total (355ms).
[10:07:10.407] <TB1> INFO: Test took 1486ms.
[10:07:10.411] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:10.824] <TB1> INFO: Expecting 2560 events.
[10:07:11.897] <TB1> INFO: 2560 events read in total (356ms).
[10:07:11.898] <TB1> INFO: Test took 1487ms.
[10:07:11.901] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:12.314] <TB1> INFO: Expecting 2560 events.
[10:07:13.383] <TB1> INFO: 2560 events read in total (352ms).
[10:07:13.383] <TB1> INFO: Test took 1482ms.
[10:07:13.386] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:13.800] <TB1> INFO: Expecting 2560 events.
[10:07:14.871] <TB1> INFO: 2560 events read in total (354ms).
[10:07:14.872] <TB1> INFO: Test took 1486ms.
[10:07:14.875] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:15.289] <TB1> INFO: Expecting 2560 events.
[10:07:16.361] <TB1> INFO: 2560 events read in total (355ms).
[10:07:16.361] <TB1> INFO: Test took 1487ms.
[10:07:16.369] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:16.778] <TB1> INFO: Expecting 2560 events.
[10:07:17.851] <TB1> INFO: 2560 events read in total (356ms).
[10:07:17.851] <TB1> INFO: Test took 1482ms.
[10:07:17.854] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:18.267] <TB1> INFO: Expecting 2560 events.
[10:07:19.336] <TB1> INFO: 2560 events read in total (352ms).
[10:07:19.336] <TB1> INFO: Test took 1482ms.
[10:07:19.339] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:19.753] <TB1> INFO: Expecting 2560 events.
[10:07:20.826] <TB1> INFO: 2560 events read in total (356ms).
[10:07:20.826] <TB1> INFO: Test took 1487ms.
[10:07:20.829] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:21.243] <TB1> INFO: Expecting 2560 events.
[10:07:22.307] <TB1> INFO: 2560 events read in total (348ms).
[10:07:22.307] <TB1> INFO: Test took 1478ms.
[10:07:22.310] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:22.724] <TB1> INFO: Expecting 2560 events.
[10:07:23.798] <TB1> INFO: 2560 events read in total (357ms).
[10:07:23.798] <TB1> INFO: Test took 1488ms.
[10:07:23.801] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:24.216] <TB1> INFO: Expecting 2560 events.
[10:07:25.289] <TB1> INFO: 2560 events read in total (356ms).
[10:07:25.289] <TB1> INFO: Test took 1488ms.
[10:07:25.292] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:07:25.706] <TB1> INFO: Expecting 2560 events.
[10:07:26.778] <TB1> INFO: 2560 events read in total (355ms).
[10:07:26.778] <TB1> INFO: Test took 1486ms.
[10:07:27.467] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 613 seconds
[10:07:27.467] <TB1> INFO: PH scale (per ROC): 81 78 93 80 80 86 76 80 87 81 84 75 95 75 78 82
[10:07:27.467] <TB1> INFO: PH offset (per ROC): 177 156 159 173 165 167 172 151 140 161 156 150 147 161 156 149
[10:07:27.647] <TB1> INFO: ######################################################################
[10:07:27.647] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[10:07:27.647] <TB1> INFO: ######################################################################
[10:07:27.658] <TB1> INFO: scanning low vcal = 10
[10:07:27.963] <TB1> INFO: Expecting 41600 events.
[10:07:31.586] <TB1> INFO: 41600 events read in total (2906ms).
[10:07:31.586] <TB1> INFO: Test took 3928ms.
[10:07:31.591] <TB1> INFO: scanning low vcal = 20
[10:07:32.002] <TB1> INFO: Expecting 41600 events.
[10:07:35.631] <TB1> INFO: 41600 events read in total (2912ms).
[10:07:35.631] <TB1> INFO: Test took 4040ms.
[10:07:35.634] <TB1> INFO: scanning low vcal = 30
[10:07:36.048] <TB1> INFO: Expecting 41600 events.
[10:07:39.723] <TB1> INFO: 41600 events read in total (2958ms).
[10:07:39.724] <TB1> INFO: Test took 4090ms.
[10:07:39.728] <TB1> INFO: scanning low vcal = 40
[10:07:40.131] <TB1> INFO: Expecting 41600 events.
[10:07:44.372] <TB1> INFO: 41600 events read in total (3524ms).
[10:07:44.373] <TB1> INFO: Test took 4645ms.
[10:07:44.377] <TB1> INFO: scanning low vcal = 50
[10:07:44.724] <TB1> INFO: Expecting 41600 events.
[10:07:48.934] <TB1> INFO: 41600 events read in total (3493ms).
[10:07:48.935] <TB1> INFO: Test took 4558ms.
[10:07:48.938] <TB1> INFO: scanning low vcal = 60
[10:07:49.279] <TB1> INFO: Expecting 41600 events.
[10:07:53.518] <TB1> INFO: 41600 events read in total (3522ms).
[10:07:53.518] <TB1> INFO: Test took 4580ms.
[10:07:53.522] <TB1> INFO: scanning low vcal = 70
[10:07:53.868] <TB1> INFO: Expecting 41600 events.
[10:07:58.081] <TB1> INFO: 41600 events read in total (3496ms).
[10:07:58.082] <TB1> INFO: Test took 4560ms.
[10:07:58.085] <TB1> INFO: scanning low vcal = 80
[10:07:58.434] <TB1> INFO: Expecting 41600 events.
[10:08:02.497] <TB1> INFO: 41600 events read in total (3346ms).
[10:08:02.497] <TB1> INFO: Test took 4412ms.
[10:08:02.501] <TB1> INFO: scanning low vcal = 90
[10:08:02.852] <TB1> INFO: Expecting 41600 events.
[10:08:07.021] <TB1> INFO: 41600 events read in total (3452ms).
[10:08:07.021] <TB1> INFO: Test took 4520ms.
[10:08:07.025] <TB1> INFO: scanning low vcal = 100
[10:08:07.381] <TB1> INFO: Expecting 41600 events.
[10:08:11.463] <TB1> INFO: 41600 events read in total (3365ms).
[10:08:11.464] <TB1> INFO: Test took 4439ms.
[10:08:11.467] <TB1> INFO: scanning low vcal = 110
[10:08:11.816] <TB1> INFO: Expecting 41600 events.
[10:08:15.881] <TB1> INFO: 41600 events read in total (3348ms).
[10:08:15.882] <TB1> INFO: Test took 4415ms.
[10:08:15.885] <TB1> INFO: scanning low vcal = 120
[10:08:16.236] <TB1> INFO: Expecting 41600 events.
[10:08:20.297] <TB1> INFO: 41600 events read in total (3345ms).
[10:08:20.298] <TB1> INFO: Test took 4413ms.
[10:08:20.301] <TB1> INFO: scanning low vcal = 130
[10:08:20.646] <TB1> INFO: Expecting 41600 events.
[10:08:24.700] <TB1> INFO: 41600 events read in total (3337ms).
[10:08:24.701] <TB1> INFO: Test took 4400ms.
[10:08:24.704] <TB1> INFO: scanning low vcal = 140
[10:08:25.051] <TB1> INFO: Expecting 41600 events.
[10:08:29.264] <TB1> INFO: 41600 events read in total (3496ms).
[10:08:29.264] <TB1> INFO: Test took 4560ms.
[10:08:29.268] <TB1> INFO: scanning low vcal = 150
[10:08:29.614] <TB1> INFO: Expecting 41600 events.
[10:08:33.677] <TB1> INFO: 41600 events read in total (3346ms).
[10:08:33.677] <TB1> INFO: Test took 4409ms.
[10:08:33.681] <TB1> INFO: scanning low vcal = 160
[10:08:34.024] <TB1> INFO: Expecting 41600 events.
[10:08:38.090] <TB1> INFO: 41600 events read in total (3349ms).
[10:08:38.091] <TB1> INFO: Test took 4410ms.
[10:08:38.095] <TB1> INFO: scanning low vcal = 170
[10:08:38.437] <TB1> INFO: Expecting 41600 events.
[10:08:42.470] <TB1> INFO: 41600 events read in total (3316ms).
[10:08:42.471] <TB1> INFO: Test took 4376ms.
[10:08:42.476] <TB1> INFO: scanning low vcal = 180
[10:08:42.830] <TB1> INFO: Expecting 41600 events.
[10:08:46.869] <TB1> INFO: 41600 events read in total (3323ms).
[10:08:46.870] <TB1> INFO: Test took 4394ms.
[10:08:46.874] <TB1> INFO: scanning low vcal = 190
[10:08:47.222] <TB1> INFO: Expecting 41600 events.
[10:08:51.272] <TB1> INFO: 41600 events read in total (3333ms).
[10:08:51.273] <TB1> INFO: Test took 4399ms.
[10:08:51.276] <TB1> INFO: scanning low vcal = 200
[10:08:51.631] <TB1> INFO: Expecting 41600 events.
[10:08:55.770] <TB1> INFO: 41600 events read in total (3422ms).
[10:08:55.771] <TB1> INFO: Test took 4495ms.
[10:08:55.774] <TB1> INFO: scanning low vcal = 210
[10:08:56.109] <TB1> INFO: Expecting 41600 events.
[10:09:00.289] <TB1> INFO: 41600 events read in total (3463ms).
[10:09:00.289] <TB1> INFO: Test took 4515ms.
[10:09:00.293] <TB1> INFO: scanning low vcal = 220
[10:09:00.642] <TB1> INFO: Expecting 41600 events.
[10:09:04.790] <TB1> INFO: 41600 events read in total (3431ms).
[10:09:04.790] <TB1> INFO: Test took 4497ms.
[10:09:04.794] <TB1> INFO: scanning low vcal = 230
[10:09:05.149] <TB1> INFO: Expecting 41600 events.
[10:09:09.348] <TB1> INFO: 41600 events read in total (3482ms).
[10:09:09.348] <TB1> INFO: Test took 4554ms.
[10:09:09.352] <TB1> INFO: scanning low vcal = 240
[10:09:09.703] <TB1> INFO: Expecting 41600 events.
[10:09:13.892] <TB1> INFO: 41600 events read in total (3472ms).
[10:09:13.893] <TB1> INFO: Test took 4541ms.
[10:09:13.896] <TB1> INFO: scanning low vcal = 250
[10:09:14.239] <TB1> INFO: Expecting 41600 events.
[10:09:18.442] <TB1> INFO: 41600 events read in total (3486ms).
[10:09:18.443] <TB1> INFO: Test took 4547ms.
[10:09:18.448] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[10:09:18.796] <TB1> INFO: Expecting 41600 events.
[10:09:23.013] <TB1> INFO: 41600 events read in total (3500ms).
[10:09:23.013] <TB1> INFO: Test took 4565ms.
[10:09:23.017] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[10:09:23.364] <TB1> INFO: Expecting 41600 events.
[10:09:27.557] <TB1> INFO: 41600 events read in total (3476ms).
[10:09:27.557] <TB1> INFO: Test took 4540ms.
[10:09:27.561] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[10:09:27.909] <TB1> INFO: Expecting 41600 events.
[10:09:32.257] <TB1> INFO: 41600 events read in total (3508ms).
[10:09:32.258] <TB1> INFO: Test took 4697ms.
[10:09:32.262] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[10:09:32.606] <TB1> INFO: Expecting 41600 events.
[10:09:36.948] <TB1> INFO: 41600 events read in total (3625ms).
[10:09:36.949] <TB1> INFO: Test took 4687ms.
[10:09:36.953] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[10:09:37.305] <TB1> INFO: Expecting 41600 events.
[10:09:41.524] <TB1> INFO: 41600 events read in total (3500ms).
[10:09:41.524] <TB1> INFO: Test took 4571ms.
[10:09:42.005] <TB1> INFO: PixTestGainPedestal::measure() done
[10:10:15.169] <TB1> INFO: PixTestGainPedestal::fit() done
[10:10:15.169] <TB1> INFO: non-linearity mean: 0.956 0.961 0.956 0.959 0.963 0.956 0.950 0.964 0.958 0.960 0.952 0.960 0.957 0.951 0.956 0.959
[10:10:15.169] <TB1> INFO: non-linearity RMS: 0.006 0.004 0.005 0.006 0.005 0.006 0.007 0.005 0.005 0.005 0.005 0.006 0.005 0.006 0.006 0.005
[10:10:15.169] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C0.dat
[10:10:15.192] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C1.dat
[10:10:15.214] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C2.dat
[10:10:15.236] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C3.dat
[10:10:15.259] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C4.dat
[10:10:15.281] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C5.dat
[10:10:15.304] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C6.dat
[10:10:15.326] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C7.dat
[10:10:15.349] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C8.dat
[10:10:15.371] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C9.dat
[10:10:15.394] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C10.dat
[10:10:15.416] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C11.dat
[10:10:15.439] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C12.dat
[10:10:15.462] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C13.dat
[10:10:15.482] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C14.dat
[10:10:15.503] <TB1> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//phCalibrationFitErr35_C15.dat
[10:10:15.523] <TB1> INFO: PixTestGainPedestal::doTest() done, duration: 167 seconds
[10:10:15.530] <TB1> INFO: readReadbackCal: /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C0.dat .. /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C15.dat
[10:10:15.571] <TB1> INFO: PixTestReadback::doTest() start.
[10:10:15.572] <TB1> INFO: PixTestReadback::RES sent once
[10:10:39.601] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C0.dat
[10:10:39.601] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C1.dat
[10:10:39.601] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C2.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C3.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C4.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C5.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C6.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C7.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C8.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C9.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C10.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C11.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C12.dat
[10:10:39.602] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C13.dat
[10:10:39.603] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C14.dat
[10:10:39.603] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C15.dat
[10:10:39.651] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:10:39.651] <TB1> INFO: PixTestReadback::RES sent once
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C0.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C1.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C2.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C3.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C4.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C5.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C6.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C7.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C8.dat
[10:11:01.475] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C9.dat
[10:11:01.476] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C10.dat
[10:11:01.476] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C11.dat
[10:11:01.476] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C12.dat
[10:11:01.476] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C13.dat
[10:11:01.476] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C14.dat
[10:11:01.476] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C15.dat
[10:11:01.527] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:11:01.528] <TB1> INFO: PixTestReadback::RES sent once
[10:11:18.460] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:11:18.460] <TB1> INFO: Vbg will be calibrated using Vd calibration
[10:11:18.460] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 163calibrated Vbg = 1.18728 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.8calibrated Vbg = 1.18797 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 153calibrated Vbg = 1.19569 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 147.2calibrated Vbg = 1.20269 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 163.5calibrated Vbg = 1.20085 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 148.2calibrated Vbg = 1.20015 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 146.4calibrated Vbg = 1.20601 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.9calibrated Vbg = 1.20148 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 151.5calibrated Vbg = 1.19872 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 149.7calibrated Vbg = 1.19301 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 150.2calibrated Vbg = 1.19095 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 150.9calibrated Vbg = 1.19385 :::*/*/*/*/
[10:11:18.461] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 255calibrated Vbg = 1.1775 :::*/*/*/*/
[10:11:18.464] <TB1> INFO: PixTestReadback::RES sent once
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C0.dat
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C1.dat
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C2.dat
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C3.dat
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C4.dat
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C5.dat
[10:15:59.760] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C6.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C7.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C8.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C9.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C10.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C11.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C12.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C13.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C14.dat
[10:15:59.761] <TB1> INFO: write readback calibration parameters into /usr/local/coldboxDATA/M2052_FullQualification_2015-09-03_10h31m_1441269084//000_FulltestPxar_m20//readbackCal_C15.dat
[10:15:59.806] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[10:15:59.808] <TB1> INFO: PixTestReadback::doTest() done
[10:15:59.823] <TB1> INFO: enter test to run
[10:15:59.823] <TB1> INFO: test: exit no parameter change
[10:16:00.394] <TB1> QUIET: Connection to board 153 closed.
[10:16:00.473] <TB1> INFO: pXar: this is the end, my friend