[12:38:30.068] <TB1> INFO: *** Welcome to pxar ***
[12:38:30.068] <TB1> INFO: *** Today: 2016/10/19
[12:38:30.074] <TB1> INFO: *** Version: c8ba-dirty
[12:38:30.074] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C15.dat
[12:38:30.075] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//tbmParameters_C1b.dat
[12:38:30.075] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//defaultMaskFile.dat
[12:38:30.075] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters_C15.dat
[12:38:30.136] <TB1> INFO: clk: 4
[12:38:30.136] <TB1> INFO: ctr: 4
[12:38:30.136] <TB1> INFO: sda: 19
[12:38:30.136] <TB1> INFO: tin: 9
[12:38:30.136] <TB1> INFO: level: 15
[12:38:30.136] <TB1> INFO: triggerdelay: 0
[12:38:30.136] <TB1> QUIET: Instanciating API for pxar v2.7.6+55~gafdbfd9
[12:38:30.136] <TB1> INFO: Log level: INFO
[12:38:30.144] <TB1> INFO: Found DTB DTB_WXC03A
[12:38:30.155] <TB1> QUIET: Connection to board DTB_WXC03A opened.
[12:38:30.157] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 154
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXC03A
MAC address: 40D85511809A
Hostname: pixelDTB154
Comment:
------------------------------------------------------
[12:38:30.159] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[12:38:31.718] <TB1> INFO: DUT info:
[12:38:31.718] <TB1> INFO: The DUT currently contains the following objects:
[12:38:31.718] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[12:38:31.718] <TB1> INFO: TBM Core alpha (0): 7 registers set
[12:38:31.718] <TB1> INFO: TBM Core beta (1): 7 registers set
[12:38:31.718] <TB1> INFO: TBM Core alpha (2): 7 registers set
[12:38:31.718] <TB1> INFO: TBM Core beta (3): 7 registers set
[12:38:31.718] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:38:31.718] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:31.718] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:38:32.119] <TB1> INFO: enter 'restricted' command line mode
[12:38:32.119] <TB1> INFO: enter test to run
[12:38:32.119] <TB1> INFO: test: pretest no parameter change
[12:38:32.119] <TB1> INFO: running: pretest
[12:38:32.124] <TB1> INFO: ######################################################################
[12:38:32.124] <TB1> INFO: PixTestPretest::doTest()
[12:38:32.124] <TB1> INFO: ######################################################################
[12:38:32.125] <TB1> INFO: ----------------------------------------------------------------------
[12:38:32.125] <TB1> INFO: PixTestPretest::programROC()
[12:38:32.125] <TB1> INFO: ----------------------------------------------------------------------
[12:38:50.139] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:38:50.139] <TB1> INFO: IA differences per ROC: 16.9 16.9 18.5 18.5 16.1 17.7 17.7 19.3 18.5 20.1 18.5 19.3 16.9 18.5 19.3 16.9
[12:38:50.199] <TB1> INFO: ----------------------------------------------------------------------
[12:38:50.199] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:38:50.199] <TB1> INFO: ----------------------------------------------------------------------
[12:39:11.493] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 396.3 mA = 24.7688 mA/ROC
[12:39:11.493] <TB1> INFO: i(loss) [mA/ROC]: 20.1 20.1 19.3 17.7 19.3 19.3 20.9 19.3 21.7 19.3 20.9 19.3 19.3 20.9 19.3 19.3
[12:39:11.527] <TB1> INFO: ----------------------------------------------------------------------
[12:39:11.527] <TB1> INFO: PixTestPretest::findTiming()
[12:39:11.527] <TB1> INFO: ----------------------------------------------------------------------
[12:39:11.527] <TB1> INFO: PixTestCmd::init()

[12:39:44.063] <TB1> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:39:44.063] <TB1> INFO: (success/tries = 100/100), width = 4
[12:39:45.565] <TB1> INFO: ----------------------------------------------------------------------
[12:39:45.565] <TB1> INFO: PixTestPretest::findWorkingPixel()
[12:39:45.565] <TB1> INFO: ----------------------------------------------------------------------
[12:39:45.661] <TB1> INFO: Expecting 231680 events.
[12:39:55.701] <TB1> INFO: 231680 events read in total (9448ms).
[12:39:55.708] <TB1> INFO: Test took 10137ms.
[12:39:55.959] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:39:55.995] <TB1> INFO: ----------------------------------------------------------------------
[12:39:55.995] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[12:39:55.995] <TB1> INFO: ----------------------------------------------------------------------
[12:39:56.091] <TB1> INFO: Expecting 231680 events.
[12:40:05.956] <TB1> INFO: 231680 events read in total (9273ms).
[12:40:05.966] <TB1> INFO: Test took 9965ms.
[12:40:06.217] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[12:40:06.217] <TB1> INFO: CalDel: 67 87 92 97 66 91 77 78 91 84 83 91 84 91 98 83
[12:40:06.217] <TB1> INFO: VthrComp: 51 51 51 51 51 51 53 51 51 51 54 51 51 51 51 55
[12:40:06.220] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C0.dat
[12:40:06.220] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C1.dat
[12:40:06.220] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C2.dat
[12:40:06.220] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C3.dat
[12:40:06.220] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C4.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C5.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C6.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C7.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C8.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C9.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C10.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C11.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C12.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C13.dat
[12:40:06.221] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C14.dat
[12:40:06.222] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters_C15.dat
[12:40:06.222] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//tbmParameters_C0a.dat
[12:40:06.222] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//tbmParameters_C0b.dat
[12:40:06.222] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//tbmParameters_C1a.dat
[12:40:06.222] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//tbmParameters_C1b.dat
[12:40:06.222] <TB1> INFO: PixTestPretest::doTest() done, duration: 94 seconds
[12:40:06.273] <TB1> INFO: enter test to run
[12:40:06.273] <TB1> INFO: test: FullTest no parameter change
[12:40:06.273] <TB1> INFO: running: fulltest
[12:40:06.273] <TB1> INFO: ######################################################################
[12:40:06.273] <TB1> INFO: PixTestFullTest::doTest()
[12:40:06.273] <TB1> INFO: ######################################################################
[12:40:06.274] <TB1> INFO: ######################################################################
[12:40:06.274] <TB1> INFO: PixTestAlive::doTest()
[12:40:06.274] <TB1> INFO: ######################################################################
[12:40:06.276] <TB1> INFO: ----------------------------------------------------------------------
[12:40:06.276] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:40:06.276] <TB1> INFO: ----------------------------------------------------------------------
[12:40:06.514] <TB1> INFO: Expecting 41600 events.
[12:40:10.016] <TB1> INFO: 41600 events read in total (2910ms).
[12:40:10.017] <TB1> INFO: Test took 3740ms.
[12:40:10.254] <TB1> INFO: PixTestAlive::aliveTest() done
[12:40:10.254] <TB1> INFO: number of dead pixels (per ROC): 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1
[12:40:10.255] <TB1> INFO: ----------------------------------------------------------------------
[12:40:10.255] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:40:10.255] <TB1> INFO: ----------------------------------------------------------------------
[12:40:10.545] <TB1> INFO: Expecting 41600 events.
[12:40:13.508] <TB1> INFO: 41600 events read in total (2371ms).
[12:40:13.508] <TB1> INFO: Test took 3251ms.
[12:40:13.508] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:40:13.750] <TB1> INFO: PixTestAlive::maskTest() done
[12:40:13.750] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:40:13.751] <TB1> INFO: ----------------------------------------------------------------------
[12:40:13.751] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:40:13.751] <TB1> INFO: ----------------------------------------------------------------------
[12:40:13.995] <TB1> INFO: Expecting 41600 events.
[12:40:17.634] <TB1> INFO: 41600 events read in total (3047ms).
[12:40:17.635] <TB1> INFO: Test took 3882ms.
[12:40:17.875] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[12:40:17.875] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:40:17.875] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:40:17.875] <TB1> INFO: Decoding statistics:
[12:40:17.875] <TB1> INFO: General information:
[12:40:17.875] <TB1> INFO: 16bit words read: 0
[12:40:17.875] <TB1> INFO: valid events total: 0
[12:40:17.875] <TB1> INFO: empty events: 0
[12:40:17.875] <TB1> INFO: valid events with pixels: 0
[12:40:17.875] <TB1> INFO: valid pixel hits: 0
[12:40:17.875] <TB1> INFO: Event errors: 0
[12:40:17.875] <TB1> INFO: start marker: 0
[12:40:17.875] <TB1> INFO: stop marker: 0
[12:40:17.875] <TB1> INFO: overflow: 0
[12:40:17.875] <TB1> INFO: invalid 5bit words: 0
[12:40:17.875] <TB1> INFO: invalid XOR eye diagram: 0
[12:40:17.875] <TB1> INFO: frame (failed synchr.): 0
[12:40:17.875] <TB1> INFO: idle data (no TBM trl): 0
[12:40:17.875] <TB1> INFO: no data (only TBM hdr): 0
[12:40:17.876] <TB1> INFO: TBM errors: 0
[12:40:17.876] <TB1> INFO: flawed TBM headers: 0
[12:40:17.876] <TB1> INFO: flawed TBM trailers: 0
[12:40:17.876] <TB1> INFO: event ID mismatches: 0
[12:40:17.876] <TB1> INFO: ROC errors: 0
[12:40:17.876] <TB1> INFO: missing ROC header(s): 0
[12:40:17.876] <TB1> INFO: misplaced readback start: 0
[12:40:17.876] <TB1> INFO: Pixel decoding errors: 0
[12:40:17.876] <TB1> INFO: pixel data incomplete: 0
[12:40:17.876] <TB1> INFO: pixel address: 0
[12:40:17.876] <TB1> INFO: pulse height fill bit: 0
[12:40:17.876] <TB1> INFO: buffer corruption: 0
[12:40:17.884] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C15.dat
[12:40:17.884] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr_C15.dat

[12:40:17.884] <TB1> INFO: ######################################################################
[12:40:17.884] <TB1> INFO: PixTestReadback::doTest()
[12:40:17.884] <TB1> INFO: ######################################################################
[12:40:17.884] <TB1> INFO: ----------------------------------------------------------------------
[12:40:17.884] <TB1> INFO: PixTestReadback::CalibrateVd()
[12:40:17.884] <TB1> INFO: ----------------------------------------------------------------------
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C0.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C1.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C2.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C3.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C4.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C5.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C6.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C7.dat
[12:40:27.859] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C8.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C9.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C10.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C11.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C12.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C13.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C14.dat
[12:40:27.860] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C15.dat
[12:40:27.894] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:40:27.894] <TB1> INFO: ----------------------------------------------------------------------
[12:40:27.894] <TB1> INFO: PixTestReadback::CalibrateVa()
[12:40:27.894] <TB1> INFO: ----------------------------------------------------------------------
[12:40:37.824] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C0.dat
[12:40:37.824] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C1.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C2.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C3.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C4.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C5.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C6.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C7.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C8.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C9.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C10.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C11.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C12.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C13.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C14.dat
[12:40:37.825] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C15.dat
[12:40:37.853] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:40:37.853] <TB1> INFO: ----------------------------------------------------------------------
[12:40:37.853] <TB1> INFO: PixTestReadback::readbackVbg()
[12:40:37.853] <TB1> INFO: ----------------------------------------------------------------------
[12:40:45.525] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:40:45.525] <TB1> INFO: ----------------------------------------------------------------------
[12:40:45.525] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[12:40:45.525] <TB1> INFO: ----------------------------------------------------------------------
[12:40:45.526] <TB1> INFO: Vbg will be calibrated using Vd calibration
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 143.3calibrated Vbg = 1.18541 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 146.7calibrated Vbg = 1.19293 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 156.6calibrated Vbg = 1.19089 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 148.1calibrated Vbg = 1.18734 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 155.2calibrated Vbg = 1.19568 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 161.1calibrated Vbg = 1.19894 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 159calibrated Vbg = 1.196 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 148.8calibrated Vbg = 1.18464 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 144.9calibrated Vbg = 1.18655 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 155calibrated Vbg = 1.18712 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 155.1calibrated Vbg = 1.18248 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.6calibrated Vbg = 1.18151 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 156.6calibrated Vbg = 1.19119 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 155.8calibrated Vbg = 1.18463 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 156.9calibrated Vbg = 1.18655 :::*/*/*/*/
[12:40:45.526] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155calibrated Vbg = 1.18634 :::*/*/*/*/
[12:40:45.529] <TB1> INFO: ----------------------------------------------------------------------
[12:40:45.530] <TB1> INFO: PixTestReadback::CalibrateIa()
[12:40:45.530] <TB1> INFO: ----------------------------------------------------------------------
[12:43:26.330] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C0.dat
[12:43:26.330] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C1.dat
[12:43:26.330] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C2.dat
[12:43:26.330] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C3.dat
[12:43:26.330] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C4.dat
[12:43:26.330] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C5.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C6.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C7.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C8.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C9.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C10.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C11.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C12.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C13.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C14.dat
[12:43:26.331] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//readbackCal_C15.dat
[12:43:26.359] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[12:43:26.361] <TB1> INFO: PixTestReadback::doTest() done
[12:43:26.361] <TB1> INFO: Decoding statistics:
[12:43:26.361] <TB1> INFO: General information:
[12:43:26.361] <TB1> INFO: 16bit words read: 1536
[12:43:26.361] <TB1> INFO: valid events total: 256
[12:43:26.361] <TB1> INFO: empty events: 256
[12:43:26.361] <TB1> INFO: valid events with pixels: 0
[12:43:26.361] <TB1> INFO: valid pixel hits: 0
[12:43:26.361] <TB1> INFO: Event errors: 0
[12:43:26.361] <TB1> INFO: start marker: 0
[12:43:26.361] <TB1> INFO: stop marker: 0
[12:43:26.361] <TB1> INFO: overflow: 0
[12:43:26.361] <TB1> INFO: invalid 5bit words: 0
[12:43:26.361] <TB1> INFO: invalid XOR eye diagram: 0
[12:43:26.361] <TB1> INFO: frame (failed synchr.): 0
[12:43:26.361] <TB1> INFO: idle data (no TBM trl): 0
[12:43:26.361] <TB1> INFO: no data (only TBM hdr): 0
[12:43:26.361] <TB1> INFO: TBM errors: 0
[12:43:26.361] <TB1> INFO: flawed TBM headers: 0
[12:43:26.361] <TB1> INFO: flawed TBM trailers: 0
[12:43:26.361] <TB1> INFO: event ID mismatches: 0
[12:43:26.361] <TB1> INFO: ROC errors: 0
[12:43:26.361] <TB1> INFO: missing ROC header(s): 0
[12:43:26.361] <TB1> INFO: misplaced readback start: 0
[12:43:26.361] <TB1> INFO: Pixel decoding errors: 0
[12:43:26.361] <TB1> INFO: pixel data incomplete: 0
[12:43:26.361] <TB1> INFO: pixel address: 0
[12:43:26.361] <TB1> INFO: pulse height fill bit: 0
[12:43:26.361] <TB1> INFO: buffer corruption: 0
[12:43:26.412] <TB1> INFO: ######################################################################
[12:43:26.412] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:43:26.412] <TB1> INFO: ######################################################################
[12:43:26.414] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:43:26.431] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[12:43:26.431] <TB1> INFO: run 1 of 1
[12:43:26.677] <TB1> INFO: Expecting 3120000 events.
[12:43:57.885] <TB1> INFO: 672805 events read in total (30616ms).











[12:44:28.177] <TB1> INFO: 1338515 events read in total (60908ms).











[12:44:58.247] <TB1> INFO: 1998675 events read in total (90978ms).











[12:45:28.133] <TB1> INFO: 2656280 events read in total (120864ms).











[12:45:49.841] <TB1> INFO: 3120000 events read in total (142572ms).
[12:45:49.919] <TB1> INFO: Test took 143488ms.
[12:46:11.936] <TB1> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 165 seconds
[12:46:11.936] <TB1> INFO: number of dead bumps (per ROC): 5 4 0 0 0 1 0 0 0 0 0 0 25 1 4 21
[12:46:11.936] <TB1> INFO: separation cut (per ROC): 110 109 107 98 108 110 122 109 116 104 124 126 108 116 105 117
[12:46:11.936] <TB1> INFO: Decoding statistics:
[12:46:11.936] <TB1> INFO: General information:
[12:46:11.936] <TB1> INFO: 16bit words read: 0
[12:46:11.936] <TB1> INFO: valid events total: 0
[12:46:11.936] <TB1> INFO: empty events: 0
[12:46:11.936] <TB1> INFO: valid events with pixels: 0
[12:46:11.936] <TB1> INFO: valid pixel hits: 0
[12:46:11.936] <TB1> INFO: Event errors: 0
[12:46:11.936] <TB1> INFO: start marker: 0
[12:46:11.936] <TB1> INFO: stop marker: 0
[12:46:11.936] <TB1> INFO: overflow: 0
[12:46:11.936] <TB1> INFO: invalid 5bit words: 0
[12:46:11.936] <TB1> INFO: invalid XOR eye diagram: 0
[12:46:11.936] <TB1> INFO: frame (failed synchr.): 0
[12:46:11.936] <TB1> INFO: idle data (no TBM trl): 0
[12:46:11.936] <TB1> INFO: no data (only TBM hdr): 0
[12:46:11.936] <TB1> INFO: TBM errors: 0
[12:46:11.936] <TB1> INFO: flawed TBM headers: 0
[12:46:11.936] <TB1> INFO: flawed TBM trailers: 0
[12:46:11.936] <TB1> INFO: event ID mismatches: 0
[12:46:11.936] <TB1> INFO: ROC errors: 0
[12:46:11.936] <TB1> INFO: missing ROC header(s): 0
[12:46:11.936] <TB1> INFO: misplaced readback start: 0
[12:46:11.936] <TB1> INFO: Pixel decoding errors: 0
[12:46:11.936] <TB1> INFO: pixel data incomplete: 0
[12:46:11.936] <TB1> INFO: pixel address: 0
[12:46:11.936] <TB1> INFO: pulse height fill bit: 0
[12:46:11.936] <TB1> INFO: buffer corruption: 0
[12:46:11.977] <TB1> INFO: ######################################################################
[12:46:11.977] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:46:11.977] <TB1> INFO: ######################################################################
[12:46:11.978] <TB1> INFO: ----------------------------------------------------------------------
[12:46:11.978] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:46:11.978] <TB1> INFO: ----------------------------------------------------------------------
[12:46:11.978] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:46:11.993] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[12:46:11.993] <TB1> INFO: run 1 of 1
[12:46:12.231] <TB1> INFO: Expecting 36608000 events.
[12:46:36.252] <TB1> INFO: 701700 events read in total (23429ms).
[12:46:59.642] <TB1> INFO: 1389000 events read in total (46819ms).
[12:47:22.902] <TB1> INFO: 2075600 events read in total (70079ms).
[12:47:46.188] <TB1> INFO: 2761300 events read in total (93365ms).
[12:48:09.649] <TB1> INFO: 3448200 events read in total (116826ms).
[12:48:32.995] <TB1> INFO: 4135400 events read in total (140172ms).
[12:48:56.398] <TB1> INFO: 4821650 events read in total (163575ms).
[12:49:19.473] <TB1> INFO: 5506250 events read in total (186650ms).
[12:49:42.501] <TB1> INFO: 6190850 events read in total (209679ms).
[12:50:06.015] <TB1> INFO: 6874950 events read in total (233192ms).
[12:50:29.177] <TB1> INFO: 7558850 events read in total (256354ms).
[12:50:52.439] <TB1> INFO: 8243250 events read in total (279616ms).
[12:51:15.469] <TB1> INFO: 8924900 events read in total (302646ms).
[12:51:38.228] <TB1> INFO: 9606250 events read in total (325405ms).
[12:52:01.248] <TB1> INFO: 10288650 events read in total (348425ms).
[12:52:24.319] <TB1> INFO: 10973600 events read in total (371496ms).
[12:52:47.808] <TB1> INFO: 11657200 events read in total (394985ms).
[12:53:11.055] <TB1> INFO: 12340800 events read in total (418232ms).
[12:53:34.076] <TB1> INFO: 13023450 events read in total (441253ms).
[12:53:57.436] <TB1> INFO: 13706150 events read in total (464613ms).
[12:54:20.762] <TB1> INFO: 14386500 events read in total (487939ms).
[12:54:43.691] <TB1> INFO: 15066100 events read in total (510868ms).
[12:55:06.685] <TB1> INFO: 15747150 events read in total (533862ms).
[12:55:30.064] <TB1> INFO: 16426600 events read in total (557241ms).
[12:55:53.067] <TB1> INFO: 17107050 events read in total (580244ms).
[12:56:16.114] <TB1> INFO: 17789400 events read in total (603291ms).
[12:56:39.032] <TB1> INFO: 18468700 events read in total (626209ms).
[12:57:01.972] <TB1> INFO: 19148000 events read in total (649149ms).
[12:57:24.934] <TB1> INFO: 19826750 events read in total (672111ms).
[12:57:48.025] <TB1> INFO: 20504450 events read in total (695202ms).
[12:58:11.094] <TB1> INFO: 21181000 events read in total (718271ms).
[12:58:33.922] <TB1> INFO: 21857300 events read in total (741099ms).
[12:58:57.008] <TB1> INFO: 22530950 events read in total (764185ms).
[12:59:19.788] <TB1> INFO: 23206300 events read in total (786965ms).
[12:59:43.158] <TB1> INFO: 23882700 events read in total (810335ms).
[13:00:06.711] <TB1> INFO: 24559000 events read in total (833888ms).
[13:00:29.831] <TB1> INFO: 25234400 events read in total (857008ms).
[13:00:52.712] <TB1> INFO: 25909900 events read in total (879889ms).
[13:01:15.859] <TB1> INFO: 26584800 events read in total (903036ms).
[13:01:38.955] <TB1> INFO: 27260350 events read in total (926132ms).
[13:02:02.250] <TB1> INFO: 27934600 events read in total (949427ms).
[13:02:25.234] <TB1> INFO: 28607700 events read in total (972411ms).
[13:02:47.976] <TB1> INFO: 29281950 events read in total (995153ms).
[13:03:10.698] <TB1> INFO: 29953900 events read in total (1017875ms).
[13:03:33.943] <TB1> INFO: 30626650 events read in total (1041120ms).
[13:03:57.397] <TB1> INFO: 31299400 events read in total (1064574ms).
[13:04:20.561] <TB1> INFO: 31970050 events read in total (1087738ms).
[13:04:43.546] <TB1> INFO: 32643100 events read in total (1110723ms).
[13:05:06.671] <TB1> INFO: 33315450 events read in total (1133848ms).
[13:05:30.139] <TB1> INFO: 33990650 events read in total (1157316ms).
[13:05:52.845] <TB1> INFO: 34665350 events read in total (1180022ms).
[13:06:15.962] <TB1> INFO: 35339900 events read in total (1203139ms).
[13:06:38.868] <TB1> INFO: 36016800 events read in total (1226045ms).
[13:06:58.797] <TB1> INFO: 36608000 events read in total (1245974ms).
[13:06:58.890] <TB1> INFO: Test took 1246897ms.
[13:06:59.407] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:01.160] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:03.489] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:05.851] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:08.279] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:10.202] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:11.649] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:13.600] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:15.496] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:17.800] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:19.908] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:21.409] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:22.931] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:24.692] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:26.636] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:28.458] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[13:07:30.300] <TB1> INFO: PixTestScurves::scurves() done
[13:07:30.300] <TB1> INFO: Vcal mean: 127.05 116.90 129.88 110.31 122.57 124.02 136.99 116.22 129.95 121.29 129.80 137.89 122.42 125.58 116.95 126.99
[13:07:30.300] <TB1> INFO: Vcal RMS: 6.68 5.95 6.22 4.52 6.57 5.79 6.08 4.88 5.78 6.42 6.16 5.85 6.15 5.59 6.08 7.61
[13:07:30.300] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1278 seconds
[13:07:30.300] <TB1> INFO: Decoding statistics:
[13:07:30.300] <TB1> INFO: General information:
[13:07:30.300] <TB1> INFO: 16bit words read: 0
[13:07:30.300] <TB1> INFO: valid events total: 0
[13:07:30.300] <TB1> INFO: empty events: 0
[13:07:30.300] <TB1> INFO: valid events with pixels: 0
[13:07:30.300] <TB1> INFO: valid pixel hits: 0
[13:07:30.300] <TB1> INFO: Event errors: 0
[13:07:30.300] <TB1> INFO: start marker: 0
[13:07:30.300] <TB1> INFO: stop marker: 0
[13:07:30.300] <TB1> INFO: overflow: 0
[13:07:30.300] <TB1> INFO: invalid 5bit words: 0
[13:07:30.300] <TB1> INFO: invalid XOR eye diagram: 0
[13:07:30.300] <TB1> INFO: frame (failed synchr.): 0
[13:07:30.300] <TB1> INFO: idle data (no TBM trl): 0
[13:07:30.300] <TB1> INFO: no data (only TBM hdr): 0
[13:07:30.300] <TB1> INFO: TBM errors: 0
[13:07:30.300] <TB1> INFO: flawed TBM headers: 0
[13:07:30.300] <TB1> INFO: flawed TBM trailers: 0
[13:07:30.300] <TB1> INFO: event ID mismatches: 0
[13:07:30.300] <TB1> INFO: ROC errors: 0
[13:07:30.300] <TB1> INFO: missing ROC header(s): 0
[13:07:30.300] <TB1> INFO: misplaced readback start: 0
[13:07:30.300] <TB1> INFO: Pixel decoding errors: 0
[13:07:30.300] <TB1> INFO: pixel data incomplete: 0
[13:07:30.300] <TB1> INFO: pixel address: 0
[13:07:30.301] <TB1> INFO: pulse height fill bit: 0
[13:07:30.301] <TB1> INFO: buffer corruption: 0
[13:07:30.393] <TB1> INFO: ######################################################################
[13:07:30.393] <TB1> INFO: PixTestTrim::doTest()
[13:07:30.393] <TB1> INFO: ######################################################################
[13:07:30.395] <TB1> INFO: ----------------------------------------------------------------------
[13:07:30.395] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:07:30.395] <TB1> INFO: ----------------------------------------------------------------------
[13:07:30.437] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:07:30.437] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:07:30.450] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:07:30.450] <TB1> INFO: run 1 of 1
[13:07:30.699] <TB1> INFO: Expecting 5025280 events.
[13:08:01.317] <TB1> INFO: 839208 events read in total (30021ms).
[13:08:32.036] <TB1> INFO: 1675568 events read in total (60740ms).
[13:09:03.109] <TB1> INFO: 2508872 events read in total (91813ms).
[13:09:33.557] <TB1> INFO: 3335896 events read in total (122261ms).
[13:10:04.238] <TB1> INFO: 4158968 events read in total (152942ms).
[13:10:34.076] <TB1> INFO: 4979520 events read in total (182780ms).
[13:10:36.151] <TB1> INFO: 5025280 events read in total (184855ms).
[13:10:36.198] <TB1> INFO: Test took 185747ms.
[13:10:51.222] <TB1> INFO: ROC 0 VthrComp = 134
[13:10:51.222] <TB1> INFO: ROC 1 VthrComp = 124
[13:10:51.222] <TB1> INFO: ROC 2 VthrComp = 133
[13:10:51.222] <TB1> INFO: ROC 3 VthrComp = 114
[13:10:51.222] <TB1> INFO: ROC 4 VthrComp = 127
[13:10:51.223] <TB1> INFO: ROC 5 VthrComp = 126
[13:10:51.223] <TB1> INFO: ROC 6 VthrComp = 141
[13:10:51.223] <TB1> INFO: ROC 7 VthrComp = 127
[13:10:51.223] <TB1> INFO: ROC 8 VthrComp = 135
[13:10:51.223] <TB1> INFO: ROC 9 VthrComp = 119
[13:10:51.223] <TB1> INFO: ROC 10 VthrComp = 135
[13:10:51.223] <TB1> INFO: ROC 11 VthrComp = 133
[13:10:51.223] <TB1> INFO: ROC 12 VthrComp = 124
[13:10:51.223] <TB1> INFO: ROC 13 VthrComp = 134
[13:10:51.223] <TB1> INFO: ROC 14 VthrComp = 117
[13:10:51.223] <TB1> INFO: ROC 15 VthrComp = 130
[13:10:51.549] <TB1> INFO: Expecting 41600 events.
[13:10:55.226] <TB1> INFO: 41600 events read in total (3086ms).
[13:10:55.226] <TB1> INFO: Test took 4001ms.
[13:10:55.235] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:10:55.236] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:10:55.247] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:10:55.247] <TB1> INFO: run 1 of 1
[13:10:55.525] <TB1> INFO: Expecting 5025280 events.
[13:11:21.737] <TB1> INFO: 592032 events read in total (25620ms).
[13:11:47.801] <TB1> INFO: 1182760 events read in total (51684ms).
[13:12:13.804] <TB1> INFO: 1773920 events read in total (77687ms).
[13:12:39.665] <TB1> INFO: 2364464 events read in total (103548ms).
[13:13:05.742] <TB1> INFO: 2952952 events read in total (129626ms).
[13:13:31.580] <TB1> INFO: 3539216 events read in total (155463ms).
[13:13:57.573] <TB1> INFO: 4124168 events read in total (181456ms).
[13:14:23.193] <TB1> INFO: 4708496 events read in total (207076ms).
[13:14:37.147] <TB1> INFO: 5025280 events read in total (221030ms).
[13:14:37.215] <TB1> INFO: Test took 221968ms.
[13:15:04.067] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 60.598 for pixel 2/68 mean/min/max = 47.6415/34.6623/60.6207
[13:15:04.067] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 58.6575 for pixel 5/20 mean/min/max = 45.6723/32.5225/58.8221
[13:15:04.068] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 61.2668 for pixel 17/0 mean/min/max = 46.6479/32.004/61.2917
[13:15:04.068] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 56.8389 for pixel 23/71 mean/min/max = 45.2714/33.5977/56.945
[13:15:04.068] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 58.5552 for pixel 24/4 mean/min/max = 45.5912/31.9845/59.198
[13:15:04.069] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 61.3493 for pixel 0/2 mean/min/max = 46.4596/31.3286/61.5906
[13:15:04.069] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 67.0202 for pixel 13/0 mean/min/max = 52.1731/36.917/67.4291
[13:15:04.069] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 55.4803 for pixel 11/74 mean/min/max = 43.6583/31.1997/56.117
[13:15:04.070] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 60.2386 for pixel 17/76 mean/min/max = 48.0241/35.8013/60.247
[13:15:04.070] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 62.1837 for pixel 4/0 mean/min/max = 47.1053/31.9253/62.2852
[13:15:04.070] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 63.347 for pixel 8/54 mean/min/max = 50.1902/36.9069/63.4736
[13:15:04.071] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 66.0535 for pixel 5/4 mean/min/max = 51.7357/37.1945/66.277
[13:15:04.071] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 60.1969 for pixel 16/5 mean/min/max = 46.6804/33.1178/60.2429
[13:15:04.071] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 57.6988 for pixel 39/5 mean/min/max = 46.6789/35.571/57.7868
[13:15:04.072] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 60.1765 for pixel 6/78 mean/min/max = 46.4929/32.7178/60.2679
[13:15:04.072] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 64.2065 for pixel 51/18 mean/min/max = 48.6601/33.0528/64.2674
[13:15:04.072] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:15:04.161] <TB1> INFO: Expecting 411648 events.
[13:15:13.603] <TB1> INFO: 411648 events read in total (8851ms).
[13:15:13.611] <TB1> INFO: Expecting 411648 events.
[13:15:22.685] <TB1> INFO: 411648 events read in total (8671ms).
[13:15:22.698] <TB1> INFO: Expecting 411648 events.
[13:15:31.853] <TB1> INFO: 411648 events read in total (8752ms).
[13:15:31.866] <TB1> INFO: Expecting 411648 events.
[13:15:41.077] <TB1> INFO: 411648 events read in total (8808ms).
[13:15:41.093] <TB1> INFO: Expecting 411648 events.
[13:15:50.387] <TB1> INFO: 411648 events read in total (8891ms).
[13:15:50.407] <TB1> INFO: Expecting 411648 events.
[13:15:59.631] <TB1> INFO: 411648 events read in total (8821ms).
[13:15:59.659] <TB1> INFO: Expecting 411648 events.
[13:16:09.005] <TB1> INFO: 411648 events read in total (8943ms).
[13:16:09.030] <TB1> INFO: Expecting 411648 events.
[13:16:18.376] <TB1> INFO: 411648 events read in total (8942ms).
[13:16:18.403] <TB1> INFO: Expecting 411648 events.
[13:16:27.779] <TB1> INFO: 411648 events read in total (8972ms).
[13:16:27.809] <TB1> INFO: Expecting 411648 events.
[13:16:37.098] <TB1> INFO: 411648 events read in total (8886ms).
[13:16:37.131] <TB1> INFO: Expecting 411648 events.
[13:16:46.448] <TB1> INFO: 411648 events read in total (8914ms).
[13:16:46.484] <TB1> INFO: Expecting 411648 events.
[13:16:55.734] <TB1> INFO: 411648 events read in total (8847ms).
[13:16:55.773] <TB1> INFO: Expecting 411648 events.
[13:17:05.156] <TB1> INFO: 411648 events read in total (8980ms).
[13:17:05.198] <TB1> INFO: Expecting 411648 events.
[13:17:14.526] <TB1> INFO: 411648 events read in total (8925ms).
[13:17:14.572] <TB1> INFO: Expecting 411648 events.
[13:17:23.970] <TB1> INFO: 411648 events read in total (8995ms).
[13:17:24.028] <TB1> INFO: Expecting 411648 events.
[13:17:33.256] <TB1> INFO: 411648 events read in total (8825ms).
[13:17:33.390] <TB1> INFO: Test took 149318ms.
[13:17:34.246] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:17:34.259] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:17:34.259] <TB1> INFO: run 1 of 1
[13:17:34.516] <TB1> INFO: Expecting 5025280 events.
[13:18:00.648] <TB1> INFO: 585688 events read in total (25541ms).
[13:18:26.528] <TB1> INFO: 1170416 events read in total (51421ms).
[13:18:52.635] <TB1> INFO: 1755760 events read in total (77528ms).
[13:19:18.745] <TB1> INFO: 2340744 events read in total (103638ms).
[13:19:45.388] <TB1> INFO: 2924600 events read in total (130281ms).
[13:20:12.013] <TB1> INFO: 3509784 events read in total (156906ms).
[13:20:39.153] <TB1> INFO: 4095424 events read in total (184046ms).
[13:21:05.456] <TB1> INFO: 4680824 events read in total (210349ms).
[13:21:21.524] <TB1> INFO: 5025280 events read in total (226417ms).
[13:21:21.663] <TB1> INFO: Test took 227404ms.
[13:21:48.822] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 11.379810 .. 146.782428
[13:21:49.058] <TB1> INFO: Expecting 208000 events.
[13:21:58.677] <TB1> INFO: 208000 events read in total (9025ms).
[13:21:58.678] <TB1> INFO: Test took 9855ms.
[13:21:58.729] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 1 .. 156 (-1/-1) hits flags = 528 (plus default)
[13:21:58.741] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:21:58.741] <TB1> INFO: run 1 of 1
[13:21:59.019] <TB1> INFO: Expecting 5191680 events.
[13:22:26.083] <TB1> INFO: 584664 events read in total (26472ms).
[13:22:51.798] <TB1> INFO: 1168584 events read in total (52187ms).
[13:23:17.537] <TB1> INFO: 1752784 events read in total (77926ms).
[13:23:43.288] <TB1> INFO: 2336904 events read in total (103677ms).
[13:24:09.241] <TB1> INFO: 2921208 events read in total (129630ms).
[13:24:35.272] <TB1> INFO: 3505296 events read in total (155661ms).
[13:25:01.245] <TB1> INFO: 4088448 events read in total (181634ms).
[13:25:27.570] <TB1> INFO: 4671672 events read in total (207959ms).
[13:25:50.486] <TB1> INFO: 5191680 events read in total (230875ms).
[13:25:50.581] <TB1> INFO: Test took 231840ms.
[13:26:15.191] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.725253 .. 46.137047
[13:26:15.447] <TB1> INFO: Expecting 208000 events.
[13:26:25.300] <TB1> INFO: 208000 events read in total (9262ms).
[13:26:25.301] <TB1> INFO: Test took 10109ms.
[13:26:25.368] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 56 (-1/-1) hits flags = 528 (plus default)
[13:26:25.382] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:26:25.382] <TB1> INFO: run 1 of 1
[13:26:25.660] <TB1> INFO: Expecting 1331200 events.
[13:26:53.840] <TB1> INFO: 656576 events read in total (27588ms).
[13:27:21.764] <TB1> INFO: 1310968 events read in total (55512ms).
[13:27:23.032] <TB1> INFO: 1331200 events read in total (56780ms).
[13:27:23.063] <TB1> INFO: Test took 57682ms.
[13:27:35.933] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 26.721089 .. 48.242913
[13:27:36.184] <TB1> INFO: Expecting 208000 events.
[13:27:46.161] <TB1> INFO: 208000 events read in total (9386ms).
[13:27:46.163] <TB1> INFO: Test took 10229ms.
[13:27:46.228] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 16 .. 58 (-1/-1) hits flags = 528 (plus default)
[13:27:46.242] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:27:46.242] <TB1> INFO: run 1 of 1
[13:27:46.522] <TB1> INFO: Expecting 1431040 events.
[13:28:14.236] <TB1> INFO: 652888 events read in total (27122ms).
[13:28:43.068] <TB1> INFO: 1305712 events read in total (55954ms).
[13:28:48.711] <TB1> INFO: 1431040 events read in total (61597ms).
[13:28:48.742] <TB1> INFO: Test took 62499ms.
[13:29:01.915] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 24.807805 .. 50.084142
[13:29:02.184] <TB1> INFO: Expecting 208000 events.
[13:29:11.891] <TB1> INFO: 208000 events read in total (9115ms).
[13:29:11.892] <TB1> INFO: Test took 9975ms.
[13:29:11.940] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 60 (-1/-1) hits flags = 528 (plus default)
[13:29:11.953] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:29:11.953] <TB1> INFO: run 1 of 1
[13:29:12.231] <TB1> INFO: Expecting 1564160 events.
[13:29:40.288] <TB1> INFO: 653840 events read in total (27465ms).
[13:30:07.973] <TB1> INFO: 1307440 events read in total (55150ms).
[13:30:18.712] <TB1> INFO: 1564160 events read in total (65889ms).
[13:30:18.747] <TB1> INFO: Test took 66795ms.
[13:30:31.858] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:30:31.858] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:30:31.871] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[13:30:31.871] <TB1> INFO: run 1 of 1
[13:30:32.111] <TB1> INFO: Expecting 1364480 events.
[13:31:00.246] <TB1> INFO: 667888 events read in total (27543ms).
[13:31:27.938] <TB1> INFO: 1335640 events read in total (55236ms).
[13:31:29.617] <TB1> INFO: 1364480 events read in total (56914ms).
[13:31:29.647] <TB1> INFO: Test took 57777ms.
[13:31:43.392] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C0.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C1.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C2.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C3.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C4.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C5.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C6.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C7.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C8.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C9.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C10.dat
[13:31:43.393] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C11.dat
[13:31:43.394] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C12.dat
[13:31:43.394] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C13.dat
[13:31:43.394] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C14.dat
[13:31:43.394] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C15.dat
[13:31:43.394] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C0.dat
[13:31:43.399] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C1.dat
[13:31:43.406] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C2.dat
[13:31:43.412] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C3.dat
[13:31:43.417] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C4.dat
[13:31:43.421] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C5.dat
[13:31:43.426] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C6.dat
[13:31:43.431] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C7.dat
[13:31:43.435] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C8.dat
[13:31:43.440] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C9.dat
[13:31:43.445] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C10.dat
[13:31:43.449] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C11.dat
[13:31:43.454] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C12.dat
[13:31:43.458] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C13.dat
[13:31:43.463] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C14.dat
[13:31:43.468] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//trimParameters35_C15.dat
[13:31:43.472] <TB1> INFO: PixTestTrim::trimTest() done
[13:31:43.472] <TB1> INFO: vtrim: 133 149 143 129 132 116 196 126 144 149 161 151 132 137 118 150
[13:31:43.472] <TB1> INFO: vthrcomp: 134 124 133 114 127 126 141 127 135 119 135 133 124 134 117 130
[13:31:43.472] <TB1> INFO: vcal mean: 35.05 34.97 35.01 34.99 34.93 34.97 35.41 34.94 34.99 35.21 35.04 35.32 34.92 34.99 34.98 35.36
[13:31:43.472] <TB1> INFO: vcal RMS: 1.12 1.14 1.19 1.03 1.30 1.09 1.64 0.97 1.03 1.40 1.24 1.43 1.01 0.97 1.10 1.55
[13:31:43.472] <TB1> INFO: bits mean: 8.53 9.76 9.48 9.42 9.51 9.41 8.23 10.32 8.16 9.65 7.87 7.97 8.99 8.48 9.30 9.38
[13:31:43.472] <TB1> INFO: bits RMS: 2.61 2.53 2.67 2.57 2.71 2.79 2.37 2.54 2.58 2.67 2.33 2.36 2.67 2.58 2.70 2.47
[13:31:43.480] <TB1> INFO: ----------------------------------------------------------------------
[13:31:43.480] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:31:43.480] <TB1> INFO: ----------------------------------------------------------------------
[13:31:43.482] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:31:43.496] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:31:43.496] <TB1> INFO: run 1 of 1
[13:31:43.732] <TB1> INFO: Expecting 4160000 events.
[13:32:16.376] <TB1> INFO: 775975 events read in total (32052ms).
[13:32:48.704] <TB1> INFO: 1545175 events read in total (64380ms).
[13:33:20.901] <TB1> INFO: 2309510 events read in total (96577ms).
[13:33:53.056] <TB1> INFO: 3068285 events read in total (128732ms).
[13:34:25.120] <TB1> INFO: 3823010 events read in total (160796ms).
[13:34:39.488] <TB1> INFO: 4160000 events read in total (175164ms).
[13:34:39.559] <TB1> INFO: Test took 176064ms.
[13:35:02.363] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:35:02.376] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:35:02.376] <TB1> INFO: run 1 of 1
[13:35:02.612] <TB1> INFO: Expecting 4326400 events.
[13:35:34.878] <TB1> INFO: 738795 events read in total (31674ms).
[13:36:06.498] <TB1> INFO: 1471975 events read in total (63294ms).
[13:36:38.263] <TB1> INFO: 2201745 events read in total (95059ms).
[13:37:09.507] <TB1> INFO: 2927390 events read in total (126303ms).
[13:37:40.935] <TB1> INFO: 3649905 events read in total (157731ms).
[13:38:10.062] <TB1> INFO: 4326400 events read in total (186858ms).
[13:38:10.134] <TB1> INFO: Test took 187757ms.
[13:38:36.023] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:38:36.037] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:38:36.037] <TB1> INFO: run 1 of 1
[13:38:36.276] <TB1> INFO: Expecting 4264000 events.
[13:39:08.231] <TB1> INFO: 743575 events read in total (31364ms).
[13:39:39.917] <TB1> INFO: 1481750 events read in total (63050ms).
[13:40:11.387] <TB1> INFO: 2215930 events read in total (94520ms).
[13:40:42.730] <TB1> INFO: 2945380 events read in total (125863ms).
[13:41:14.375] <TB1> INFO: 3672100 events read in total (157508ms).
[13:41:40.329] <TB1> INFO: 4264000 events read in total (183462ms).
[13:41:40.393] <TB1> INFO: Test took 184356ms.
[13:42:07.109] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:42:07.123] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:42:07.123] <TB1> INFO: run 1 of 1
[13:42:07.403] <TB1> INFO: Expecting 4326400 events.
[13:42:39.226] <TB1> INFO: 739660 events read in total (31231ms).
[13:43:10.871] <TB1> INFO: 1473795 events read in total (62876ms).
[13:43:42.731] <TB1> INFO: 2204515 events read in total (94736ms).
[13:44:14.519] <TB1> INFO: 2930960 events read in total (126524ms).
[13:44:45.851] <TB1> INFO: 3654395 events read in total (157856ms).
[13:45:14.838] <TB1> INFO: 4326400 events read in total (186843ms).
[13:45:14.927] <TB1> INFO: Test took 187803ms.
[13:45:45.279] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[13:45:45.292] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[13:45:45.292] <TB1> INFO: run 1 of 1
[13:45:45.539] <TB1> INFO: Expecting 4284800 events.
[13:46:17.973] <TB1> INFO: 743125 events read in total (31842ms).
[13:46:49.408] <TB1> INFO: 1480535 events read in total (63277ms).
[13:47:20.814] <TB1> INFO: 2214280 events read in total (94683ms).
[13:47:52.287] <TB1> INFO: 2943570 events read in total (126156ms).
[13:48:23.665] <TB1> INFO: 3669765 events read in total (157534ms).
[13:48:50.650] <TB1> INFO: 4284800 events read in total (184519ms).
[13:48:50.717] <TB1> INFO: Test took 185424ms.
[13:49:17.076] <TB1> INFO: PixTestTrim::trimBitTest() done
[13:49:17.077] <TB1> INFO: PixTestTrim::doTest() done, duration: 2506 seconds
[13:49:17.077] <TB1> INFO: Decoding statistics:
[13:49:17.077] <TB1> INFO: General information:
[13:49:17.077] <TB1> INFO: 16bit words read: 0
[13:49:17.077] <TB1> INFO: valid events total: 0
[13:49:17.077] <TB1> INFO: empty events: 0
[13:49:17.078] <TB1> INFO: valid events with pixels: 0
[13:49:17.078] <TB1> INFO: valid pixel hits: 0
[13:49:17.078] <TB1> INFO: Event errors: 0
[13:49:17.078] <TB1> INFO: start marker: 0
[13:49:17.078] <TB1> INFO: stop marker: 0
[13:49:17.078] <TB1> INFO: overflow: 0
[13:49:17.078] <TB1> INFO: invalid 5bit words: 0
[13:49:17.078] <TB1> INFO: invalid XOR eye diagram: 0
[13:49:17.078] <TB1> INFO: frame (failed synchr.): 0
[13:49:17.078] <TB1> INFO: idle data (no TBM trl): 0
[13:49:17.078] <TB1> INFO: no data (only TBM hdr): 0
[13:49:17.078] <TB1> INFO: TBM errors: 0
[13:49:17.078] <TB1> INFO: flawed TBM headers: 0
[13:49:17.078] <TB1> INFO: flawed TBM trailers: 0
[13:49:17.078] <TB1> INFO: event ID mismatches: 0
[13:49:17.078] <TB1> INFO: ROC errors: 0
[13:49:17.078] <TB1> INFO: missing ROC header(s): 0
[13:49:17.078] <TB1> INFO: misplaced readback start: 0
[13:49:17.078] <TB1> INFO: Pixel decoding errors: 0
[13:49:17.078] <TB1> INFO: pixel data incomplete: 0
[13:49:17.078] <TB1> INFO: pixel address: 0
[13:49:17.078] <TB1> INFO: pulse height fill bit: 0
[13:49:17.078] <TB1> INFO: buffer corruption: 0
[13:49:17.709] <TB1> INFO: ######################################################################
[13:49:17.709] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[13:49:17.709] <TB1> INFO: ######################################################################
[13:49:17.951] <TB1> INFO: Expecting 41600 events.
[13:49:21.481] <TB1> INFO: 41600 events read in total (2938ms).
[13:49:21.482] <TB1> INFO: Test took 3771ms.
[13:49:21.923] <TB1> INFO: Expecting 41600 events.
[13:49:25.484] <TB1> INFO: 41600 events read in total (2970ms).
[13:49:25.486] <TB1> INFO: Test took 3801ms.
[13:49:25.776] <TB1> INFO: Expecting 41600 events.
[13:49:29.351] <TB1> INFO: 41600 events read in total (2983ms).
[13:49:29.352] <TB1> INFO: Test took 3841ms.
[13:49:29.642] <TB1> INFO: Expecting 41600 events.
[13:49:33.101] <TB1> INFO: 41600 events read in total (2868ms).
[13:49:33.102] <TB1> INFO: Test took 3725ms.
[13:49:33.392] <TB1> INFO: Expecting 41600 events.
[13:49:36.897] <TB1> INFO: 41600 events read in total (2914ms).
[13:49:36.899] <TB1> INFO: Test took 3772ms.
[13:49:37.188] <TB1> INFO: Expecting 41600 events.
[13:49:40.848] <TB1> INFO: 41600 events read in total (3068ms).
[13:49:40.849] <TB1> INFO: Test took 3925ms.
[13:49:41.145] <TB1> INFO: Expecting 41600 events.
[13:49:44.655] <TB1> INFO: 41600 events read in total (2918ms).
[13:49:44.656] <TB1> INFO: Test took 3780ms.
[13:49:44.945] <TB1> INFO: Expecting 41600 events.
[13:49:48.500] <TB1> INFO: 41600 events read in total (2963ms).
[13:49:48.502] <TB1> INFO: Test took 3822ms.
[13:49:48.793] <TB1> INFO: Expecting 41600 events.
[13:49:52.245] <TB1> INFO: 41600 events read in total (2861ms).
[13:49:52.247] <TB1> INFO: Test took 3719ms.
[13:49:52.536] <TB1> INFO: Expecting 41600 events.
[13:49:56.037] <TB1> INFO: 41600 events read in total (2910ms).
[13:49:56.039] <TB1> INFO: Test took 3768ms.
[13:49:56.330] <TB1> INFO: Expecting 41600 events.
[13:49:59.947] <TB1> INFO: 41600 events read in total (3025ms).
[13:49:59.948] <TB1> INFO: Test took 3883ms.
[13:50:00.240] <TB1> INFO: Expecting 41600 events.
[13:50:03.852] <TB1> INFO: 41600 events read in total (3020ms).
[13:50:03.853] <TB1> INFO: Test took 3878ms.
[13:50:04.145] <TB1> INFO: Expecting 41600 events.
[13:50:07.620] <TB1> INFO: 41600 events read in total (2884ms).
[13:50:07.621] <TB1> INFO: Test took 3741ms.
[13:50:07.912] <TB1> INFO: Expecting 41600 events.
[13:50:11.426] <TB1> INFO: 41600 events read in total (2922ms).
[13:50:11.427] <TB1> INFO: Test took 3780ms.
[13:50:11.716] <TB1> INFO: Expecting 41600 events.
[13:50:15.249] <TB1> INFO: 41600 events read in total (2941ms).
[13:50:15.250] <TB1> INFO: Test took 3799ms.
[13:50:15.545] <TB1> INFO: Expecting 41600 events.
[13:50:19.101] <TB1> INFO: 41600 events read in total (2964ms).
[13:50:19.102] <TB1> INFO: Test took 3825ms.
[13:50:19.394] <TB1> INFO: Expecting 41600 events.
[13:50:22.978] <TB1> INFO: 41600 events read in total (2993ms).
[13:50:22.979] <TB1> INFO: Test took 3850ms.
[13:50:23.270] <TB1> INFO: Expecting 41600 events.
[13:50:26.809] <TB1> INFO: 41600 events read in total (2947ms).
[13:50:26.810] <TB1> INFO: Test took 3804ms.
[13:50:27.102] <TB1> INFO: Expecting 41600 events.
[13:50:30.664] <TB1> INFO: 41600 events read in total (2971ms).
[13:50:30.665] <TB1> INFO: Test took 3828ms.
[13:50:30.954] <TB1> INFO: Expecting 41600 events.
[13:50:34.518] <TB1> INFO: 41600 events read in total (2972ms).
[13:50:34.519] <TB1> INFO: Test took 3830ms.
[13:50:34.808] <TB1> INFO: Expecting 41600 events.
[13:50:38.282] <TB1> INFO: 41600 events read in total (2883ms).
[13:50:38.283] <TB1> INFO: Test took 3740ms.
[13:50:38.572] <TB1> INFO: Expecting 41600 events.
[13:50:42.037] <TB1> INFO: 41600 events read in total (2874ms).
[13:50:42.038] <TB1> INFO: Test took 3731ms.
[13:50:42.327] <TB1> INFO: Expecting 41600 events.
[13:50:45.799] <TB1> INFO: 41600 events read in total (2880ms).
[13:50:45.800] <TB1> INFO: Test took 3737ms.
[13:50:46.089] <TB1> INFO: Expecting 41600 events.
[13:50:49.553] <TB1> INFO: 41600 events read in total (2872ms).
[13:50:49.554] <TB1> INFO: Test took 3729ms.
[13:50:49.842] <TB1> INFO: Expecting 41600 events.
[13:50:53.329] <TB1> INFO: 41600 events read in total (2895ms).
[13:50:53.330] <TB1> INFO: Test took 3752ms.
[13:50:53.618] <TB1> INFO: Expecting 41600 events.
[13:50:57.082] <TB1> INFO: 41600 events read in total (2872ms).
[13:50:57.083] <TB1> INFO: Test took 3729ms.
[13:50:57.374] <TB1> INFO: Expecting 41600 events.
[13:51:00.840] <TB1> INFO: 41600 events read in total (2874ms).
[13:51:00.841] <TB1> INFO: Test took 3732ms.
[13:51:01.131] <TB1> INFO: Expecting 2560 events.
[13:51:02.019] <TB1> INFO: 2560 events read in total (297ms).
[13:51:02.019] <TB1> INFO: Test took 1165ms.
[13:51:02.329] <TB1> INFO: Expecting 2560 events.
[13:51:03.213] <TB1> INFO: 2560 events read in total (292ms).
[13:51:03.213] <TB1> INFO: Test took 1194ms.
[13:51:03.521] <TB1> INFO: Expecting 2560 events.
[13:51:04.418] <TB1> INFO: 2560 events read in total (305ms).
[13:51:04.418] <TB1> INFO: Test took 1205ms.
[13:51:04.726] <TB1> INFO: Expecting 2560 events.
[13:51:05.616] <TB1> INFO: 2560 events read in total (298ms).
[13:51:05.616] <TB1> INFO: Test took 1197ms.
[13:51:05.925] <TB1> INFO: Expecting 2560 events.
[13:51:06.804] <TB1> INFO: 2560 events read in total (288ms).
[13:51:06.805] <TB1> INFO: Test took 1188ms.
[13:51:07.112] <TB1> INFO: Expecting 2560 events.
[13:51:07.997] <TB1> INFO: 2560 events read in total (293ms).
[13:51:07.998] <TB1> INFO: Test took 1193ms.
[13:51:08.304] <TB1> INFO: Expecting 2560 events.
[13:51:09.198] <TB1> INFO: 2560 events read in total (302ms).
[13:51:09.198] <TB1> INFO: Test took 1200ms.
[13:51:09.505] <TB1> INFO: Expecting 2560 events.
[13:51:10.393] <TB1> INFO: 2560 events read in total (296ms).
[13:51:10.393] <TB1> INFO: Test took 1194ms.
[13:51:10.701] <TB1> INFO: Expecting 2560 events.
[13:51:11.582] <TB1> INFO: 2560 events read in total (289ms).
[13:51:11.582] <TB1> INFO: Test took 1189ms.
[13:51:11.890] <TB1> INFO: Expecting 2560 events.
[13:51:12.783] <TB1> INFO: 2560 events read in total (301ms).
[13:51:12.783] <TB1> INFO: Test took 1200ms.
[13:51:13.091] <TB1> INFO: Expecting 2560 events.
[13:51:13.977] <TB1> INFO: 2560 events read in total (294ms).
[13:51:13.978] <TB1> INFO: Test took 1194ms.
[13:51:14.284] <TB1> INFO: Expecting 2560 events.
[13:51:15.172] <TB1> INFO: 2560 events read in total (296ms).
[13:51:15.172] <TB1> INFO: Test took 1194ms.
[13:51:15.481] <TB1> INFO: Expecting 2560 events.
[13:51:16.373] <TB1> INFO: 2560 events read in total (301ms).
[13:51:16.374] <TB1> INFO: Test took 1202ms.
[13:51:16.682] <TB1> INFO: Expecting 2560 events.
[13:51:17.569] <TB1> INFO: 2560 events read in total (296ms).
[13:51:17.570] <TB1> INFO: Test took 1196ms.
[13:51:17.877] <TB1> INFO: Expecting 2560 events.
[13:51:18.762] <TB1> INFO: 2560 events read in total (294ms).
[13:51:18.762] <TB1> INFO: Test took 1192ms.
[13:51:19.070] <TB1> INFO: Expecting 2560 events.
[13:51:19.962] <TB1> INFO: 2560 events read in total (300ms).
[13:51:19.962] <TB1> INFO: Test took 1199ms.
[13:51:19.966] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:51:20.272] <TB1> INFO: Expecting 655360 events.
[13:51:35.080] <TB1> INFO: 655360 events read in total (14217ms).
[13:51:35.092] <TB1> INFO: Expecting 655360 events.
[13:51:49.946] <TB1> INFO: 655360 events read in total (14451ms).
[13:51:49.968] <TB1> INFO: Expecting 655360 events.
[13:52:04.777] <TB1> INFO: 655360 events read in total (14406ms).
[13:52:04.803] <TB1> INFO: Expecting 655360 events.
[13:52:19.385] <TB1> INFO: 655360 events read in total (14179ms).
[13:52:19.413] <TB1> INFO: Expecting 655360 events.
[13:52:33.921] <TB1> INFO: 655360 events read in total (14105ms).
[13:52:33.950] <TB1> INFO: Expecting 655360 events.
[13:52:48.719] <TB1> INFO: 655360 events read in total (14366ms).
[13:52:48.752] <TB1> INFO: Expecting 655360 events.
[13:53:03.433] <TB1> INFO: 655360 events read in total (14278ms).
[13:53:03.470] <TB1> INFO: Expecting 655360 events.
[13:53:18.026] <TB1> INFO: 655360 events read in total (14153ms).
[13:53:18.100] <TB1> INFO: Expecting 655360 events.
[13:53:32.529] <TB1> INFO: 655360 events read in total (14026ms).
[13:53:32.578] <TB1> INFO: Expecting 655360 events.
[13:53:47.088] <TB1> INFO: 655360 events read in total (14107ms).
[13:53:47.161] <TB1> INFO: Expecting 655360 events.
[13:54:01.646] <TB1> INFO: 655360 events read in total (14082ms).
[13:54:01.712] <TB1> INFO: Expecting 655360 events.
[13:54:16.217] <TB1> INFO: 655360 events read in total (14102ms).
[13:54:16.288] <TB1> INFO: Expecting 655360 events.
[13:54:30.737] <TB1> INFO: 655360 events read in total (14046ms).
[13:54:30.804] <TB1> INFO: Expecting 655360 events.
[13:54:45.384] <TB1> INFO: 655360 events read in total (14177ms).
[13:54:45.467] <TB1> INFO: Expecting 655360 events.
[13:54:59.900] <TB1> INFO: 655360 events read in total (14030ms).
[13:54:59.990] <TB1> INFO: Expecting 655360 events.
[13:55:14.487] <TB1> INFO: 655360 events read in total (14094ms).
[13:55:14.611] <TB1> INFO: Test took 234645ms.
[13:55:14.706] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:55:14.964] <TB1> INFO: Expecting 655360 events.
[13:55:29.328] <TB1> INFO: 655360 events read in total (13772ms).
[13:55:29.340] <TB1> INFO: Expecting 655360 events.
[13:55:43.681] <TB1> INFO: 655360 events read in total (13938ms).
[13:55:43.697] <TB1> INFO: Expecting 655360 events.
[13:55:58.178] <TB1> INFO: 655360 events read in total (14078ms).
[13:55:58.199] <TB1> INFO: Expecting 655360 events.
[13:56:12.605] <TB1> INFO: 655360 events read in total (14003ms).
[13:56:12.630] <TB1> INFO: Expecting 655360 events.
[13:56:27.249] <TB1> INFO: 655360 events read in total (14216ms).
[13:56:27.277] <TB1> INFO: Expecting 655360 events.
[13:56:41.791] <TB1> INFO: 655360 events read in total (14111ms).
[13:56:41.836] <TB1> INFO: Expecting 655360 events.
[13:56:56.204] <TB1> INFO: 655360 events read in total (13965ms).
[13:56:56.250] <TB1> INFO: Expecting 655360 events.
[13:57:10.938] <TB1> INFO: 655360 events read in total (14285ms).
[13:57:10.992] <TB1> INFO: Expecting 655360 events.
[13:57:25.156] <TB1> INFO: 655360 events read in total (13760ms).
[13:57:25.204] <TB1> INFO: Expecting 655360 events.
[13:57:39.329] <TB1> INFO: 655360 events read in total (13722ms).
[13:57:39.502] <TB1> INFO: Expecting 655360 events.
[13:57:54.017] <TB1> INFO: 655360 events read in total (14112ms).
[13:57:54.084] <TB1> INFO: Expecting 655360 events.
[13:58:08.506] <TB1> INFO: 655360 events read in total (14019ms).
[13:58:08.589] <TB1> INFO: Expecting 655360 events.
[13:58:22.554] <TB1> INFO: 655360 events read in total (13562ms).
[13:58:22.632] <TB1> INFO: Expecting 655360 events.
[13:58:37.113] <TB1> INFO: 655360 events read in total (14078ms).
[13:58:37.219] <TB1> INFO: Expecting 655360 events.
[13:58:51.221] <TB1> INFO: 655360 events read in total (13599ms).
[13:58:51.315] <TB1> INFO: Expecting 655360 events.
[13:59:05.440] <TB1> INFO: 655360 events read in total (13722ms).
[13:59:05.535] <TB1> INFO: Test took 230829ms.
[13:59:05.701] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.707] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.713] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.718] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.724] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.730] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.735] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.741] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:59:05.747] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:59:05.752] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:59:05.758] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.764] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.769] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:59:05.775] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:59:05.781] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:59:05.786] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:59:05.792] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:59:05.798] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.804] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.810] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:59:05.817] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:59:05.823] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.829] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.835] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.842] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.848] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:59:05.855] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:59:05.861] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:59:05.868] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.874] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.881] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.888] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.896] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.903] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.909] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[13:59:05.916] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[13:59:05.922] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[13:59:05.929] <TB1> INFO: safety margin for low PH: adding 4, margin is now 24
[13:59:05.936] <TB1> INFO: safety margin for low PH: adding 5, margin is now 25
[13:59:05.943] <TB1> INFO: safety margin for low PH: adding 6, margin is now 26
[13:59:05.950] <TB1> INFO: safety margin for low PH: adding 7, margin is now 27
[13:59:05.957] <TB1> INFO: safety margin for low PH: adding 8, margin is now 28
[13:59:05.963] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[13:59:05.998] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C0.dat
[13:59:05.998] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C1.dat
[13:59:05.998] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C2.dat
[13:59:05.998] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C3.dat
[13:59:05.998] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C4.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C5.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C6.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C7.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C8.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C9.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C10.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C11.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C12.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C13.dat
[13:59:05.999] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C14.dat
[13:59:05.000] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//dacParameters35_C15.dat
[13:59:06.240] <TB1> INFO: Expecting 41600 events.
[13:59:09.375] <TB1> INFO: 41600 events read in total (2544ms).
[13:59:09.376] <TB1> INFO: Test took 3374ms.
[13:59:09.836] <TB1> INFO: Expecting 41600 events.
[13:59:12.862] <TB1> INFO: 41600 events read in total (2434ms).
[13:59:12.863] <TB1> INFO: Test took 3271ms.
[13:59:13.346] <TB1> INFO: Expecting 41600 events.
[13:59:16.467] <TB1> INFO: 41600 events read in total (2529ms).
[13:59:16.467] <TB1> INFO: Test took 3393ms.
[13:59:16.686] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:16.775] <TB1> INFO: Expecting 2560 events.
[13:59:17.666] <TB1> INFO: 2560 events read in total (299ms).
[13:59:17.666] <TB1> INFO: Test took 980ms.
[13:59:17.671] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:17.974] <TB1> INFO: Expecting 2560 events.
[13:59:18.865] <TB1> INFO: 2560 events read in total (299ms).
[13:59:18.866] <TB1> INFO: Test took 1196ms.
[13:59:18.868] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:19.174] <TB1> INFO: Expecting 2560 events.
[13:59:20.062] <TB1> INFO: 2560 events read in total (296ms).
[13:59:20.062] <TB1> INFO: Test took 1194ms.
[13:59:20.064] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:20.371] <TB1> INFO: Expecting 2560 events.
[13:59:21.260] <TB1> INFO: 2560 events read in total (297ms).
[13:59:21.261] <TB1> INFO: Test took 1197ms.
[13:59:21.264] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:21.570] <TB1> INFO: Expecting 2560 events.
[13:59:22.463] <TB1> INFO: 2560 events read in total (301ms).
[13:59:22.463] <TB1> INFO: Test took 1199ms.
[13:59:22.465] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:22.772] <TB1> INFO: Expecting 2560 events.
[13:59:23.657] <TB1> INFO: 2560 events read in total (293ms).
[13:59:23.657] <TB1> INFO: Test took 1192ms.
[13:59:23.659] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:23.967] <TB1> INFO: Expecting 2560 events.
[13:59:24.863] <TB1> INFO: 2560 events read in total (304ms).
[13:59:24.863] <TB1> INFO: Test took 1204ms.
[13:59:24.866] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:25.171] <TB1> INFO: Expecting 2560 events.
[13:59:26.060] <TB1> INFO: 2560 events read in total (297ms).
[13:59:26.060] <TB1> INFO: Test took 1194ms.
[13:59:26.064] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:26.369] <TB1> INFO: Expecting 2560 events.
[13:59:27.249] <TB1> INFO: 2560 events read in total (288ms).
[13:59:27.249] <TB1> INFO: Test took 1185ms.
[13:59:27.252] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:27.558] <TB1> INFO: Expecting 2560 events.
[13:59:28.439] <TB1> INFO: 2560 events read in total (290ms).
[13:59:28.439] <TB1> INFO: Test took 1187ms.
[13:59:28.442] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:28.748] <TB1> INFO: Expecting 2560 events.
[13:59:29.633] <TB1> INFO: 2560 events read in total (293ms).
[13:59:29.633] <TB1> INFO: Test took 1191ms.
[13:59:29.635] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:29.942] <TB1> INFO: Expecting 2560 events.
[13:59:30.827] <TB1> INFO: 2560 events read in total (294ms).
[13:59:30.827] <TB1> INFO: Test took 1192ms.
[13:59:30.830] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:31.137] <TB1> INFO: Expecting 2560 events.
[13:59:32.018] <TB1> INFO: 2560 events read in total (290ms).
[13:59:32.019] <TB1> INFO: Test took 1189ms.
[13:59:32.023] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:32.327] <TB1> INFO: Expecting 2560 events.
[13:59:33.209] <TB1> INFO: 2560 events read in total (290ms).
[13:59:33.209] <TB1> INFO: Test took 1186ms.
[13:59:33.212] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:33.517] <TB1> INFO: Expecting 2560 events.
[13:59:34.404] <TB1> INFO: 2560 events read in total (295ms).
[13:59:34.405] <TB1> INFO: Test took 1193ms.
[13:59:34.408] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:34.712] <TB1> INFO: Expecting 2560 events.
[13:59:35.593] <TB1> INFO: 2560 events read in total (289ms).
[13:59:35.593] <TB1> INFO: Test took 1185ms.
[13:59:35.597] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:35.901] <TB1> INFO: Expecting 2560 events.
[13:59:36.787] <TB1> INFO: 2560 events read in total (294ms).
[13:59:36.787] <TB1> INFO: Test took 1190ms.
[13:59:36.789] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:37.096] <TB1> INFO: Expecting 2560 events.
[13:59:37.977] <TB1> INFO: 2560 events read in total (289ms).
[13:59:37.977] <TB1> INFO: Test took 1188ms.
[13:59:37.981] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:38.285] <TB1> INFO: Expecting 2560 events.
[13:59:39.176] <TB1> INFO: 2560 events read in total (299ms).
[13:59:39.176] <TB1> INFO: Test took 1196ms.
[13:59:39.180] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:39.485] <TB1> INFO: Expecting 2560 events.
[13:59:40.373] <TB1> INFO: 2560 events read in total (296ms).
[13:59:40.374] <TB1> INFO: Test took 1195ms.
[13:59:40.377] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:40.682] <TB1> INFO: Expecting 2560 events.
[13:59:41.571] <TB1> INFO: 2560 events read in total (297ms).
[13:59:41.572] <TB1> INFO: Test took 1196ms.
[13:59:41.575] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:41.880] <TB1> INFO: Expecting 2560 events.
[13:59:42.769] <TB1> INFO: 2560 events read in total (297ms).
[13:59:42.770] <TB1> INFO: Test took 1195ms.
[13:59:42.773] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:43.077] <TB1> INFO: Expecting 2560 events.
[13:59:43.966] <TB1> INFO: 2560 events read in total (297ms).
[13:59:43.966] <TB1> INFO: Test took 1193ms.
[13:59:43.969] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:44.274] <TB1> INFO: Expecting 2560 events.
[13:59:45.161] <TB1> INFO: 2560 events read in total (296ms).
[13:59:45.161] <TB1> INFO: Test took 1192ms.
[13:59:45.165] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:45.469] <TB1> INFO: Expecting 2560 events.
[13:59:46.361] <TB1> INFO: 2560 events read in total (300ms).
[13:59:46.362] <TB1> INFO: Test took 1198ms.
[13:59:46.365] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:46.670] <TB1> INFO: Expecting 2560 events.
[13:59:47.561] <TB1> INFO: 2560 events read in total (299ms).
[13:59:47.561] <TB1> INFO: Test took 1196ms.
[13:59:47.564] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:47.869] <TB1> INFO: Expecting 2560 events.
[13:59:48.760] <TB1> INFO: 2560 events read in total (299ms).
[13:59:48.760] <TB1> INFO: Test took 1196ms.
[13:59:48.763] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:49.069] <TB1> INFO: Expecting 2560 events.
[13:59:49.959] <TB1> INFO: 2560 events read in total (298ms).
[13:59:49.959] <TB1> INFO: Test took 1196ms.
[13:59:49.963] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:50.268] <TB1> INFO: Expecting 2560 events.
[13:59:51.164] <TB1> INFO: 2560 events read in total (304ms).
[13:59:51.164] <TB1> INFO: Test took 1202ms.
[13:59:51.167] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:51.471] <TB1> INFO: Expecting 2560 events.
[13:59:52.358] <TB1> INFO: 2560 events read in total (295ms).
[13:59:52.358] <TB1> INFO: Test took 1191ms.
[13:59:52.361] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:52.667] <TB1> INFO: Expecting 2560 events.
[13:59:53.557] <TB1> INFO: 2560 events read in total (298ms).
[13:59:53.558] <TB1> INFO: Test took 1197ms.
[13:59:53.561] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:59:53.866] <TB1> INFO: Expecting 2560 events.
[13:59:54.761] <TB1> INFO: 2560 events read in total (303ms).
[13:59:54.761] <TB1> INFO: Test took 1200ms.
[13:59:55.248] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 637 seconds
[13:59:55.248] <TB1> INFO: PH scale (per ROC): 37 53 49 51 62 48 33 55 36 36 43 33 49 48 39 41
[13:59:55.248] <TB1> INFO: PH offset (per ROC): 105 120 91 122 122 96 96 115 105 109 98 100 130 104 97 90
[13:59:55.258] <TB1> INFO: Decoding statistics:
[13:59:55.258] <TB1> INFO: General information:
[13:59:55.259] <TB1> INFO: 16bit words read: 127872
[13:59:55.259] <TB1> INFO: valid events total: 20480
[13:59:55.259] <TB1> INFO: empty events: 17984
[13:59:55.259] <TB1> INFO: valid events with pixels: 2496
[13:59:55.259] <TB1> INFO: valid pixel hits: 2496
[13:59:55.259] <TB1> INFO: Event errors: 0
[13:59:55.259] <TB1> INFO: start marker: 0
[13:59:55.259] <TB1> INFO: stop marker: 0
[13:59:55.259] <TB1> INFO: overflow: 0
[13:59:55.259] <TB1> INFO: invalid 5bit words: 0
[13:59:55.259] <TB1> INFO: invalid XOR eye diagram: 0
[13:59:55.259] <TB1> INFO: frame (failed synchr.): 0
[13:59:55.259] <TB1> INFO: idle data (no TBM trl): 0
[13:59:55.259] <TB1> INFO: no data (only TBM hdr): 0
[13:59:55.259] <TB1> INFO: TBM errors: 0
[13:59:55.259] <TB1> INFO: flawed TBM headers: 0
[13:59:55.259] <TB1> INFO: flawed TBM trailers: 0
[13:59:55.259] <TB1> INFO: event ID mismatches: 0
[13:59:55.259] <TB1> INFO: ROC errors: 0
[13:59:55.259] <TB1> INFO: missing ROC header(s): 0
[13:59:55.259] <TB1> INFO: misplaced readback start: 0
[13:59:55.259] <TB1> INFO: Pixel decoding errors: 0
[13:59:55.259] <TB1> INFO: pixel data incomplete: 0
[13:59:55.259] <TB1> INFO: pixel address: 0
[13:59:55.259] <TB1> INFO: pulse height fill bit: 0
[13:59:55.259] <TB1> INFO: buffer corruption: 0
[13:59:55.456] <TB1> INFO: ######################################################################
[13:59:55.456] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[13:59:55.456] <TB1> INFO: ######################################################################
[13:59:55.472] <TB1> INFO: scanning low vcal = 10
[13:59:55.710] <TB1> INFO: Expecting 41600 events.
[13:59:59.331] <TB1> INFO: 41600 events read in total (3029ms).
[13:59:59.331] <TB1> INFO: Test took 3858ms.
[13:59:59.333] <TB1> INFO: scanning low vcal = 20
[13:59:59.627] <TB1> INFO: Expecting 41600 events.
[14:00:03.213] <TB1> INFO: 41600 events read in total (2994ms).
[14:00:03.213] <TB1> INFO: Test took 3880ms.
[14:00:03.215] <TB1> INFO: scanning low vcal = 30
[14:00:03.507] <TB1> INFO: Expecting 41600 events.
[14:00:07.203] <TB1> INFO: 41600 events read in total (3104ms).
[14:00:07.204] <TB1> INFO: Test took 3989ms.
[14:00:07.207] <TB1> INFO: scanning low vcal = 40
[14:00:07.484] <TB1> INFO: Expecting 41600 events.
[14:00:11.503] <TB1> INFO: 41600 events read in total (3427ms).
[14:00:11.504] <TB1> INFO: Test took 4297ms.
[14:00:11.508] <TB1> INFO: scanning low vcal = 50
[14:00:11.784] <TB1> INFO: Expecting 41600 events.
[14:00:15.865] <TB1> INFO: 41600 events read in total (3489ms).
[14:00:15.866] <TB1> INFO: Test took 4358ms.
[14:00:15.870] <TB1> INFO: scanning low vcal = 60
[14:00:16.146] <TB1> INFO: Expecting 41600 events.
[14:00:20.145] <TB1> INFO: 41600 events read in total (3407ms).
[14:00:20.145] <TB1> INFO: Test took 4275ms.
[14:00:20.148] <TB1> INFO: scanning low vcal = 70
[14:00:20.425] <TB1> INFO: Expecting 41600 events.
[14:00:24.497] <TB1> INFO: 41600 events read in total (3480ms).
[14:00:24.498] <TB1> INFO: Test took 4349ms.
[14:00:24.502] <TB1> INFO: scanning low vcal = 80
[14:00:24.779] <TB1> INFO: Expecting 41600 events.
[14:00:28.770] <TB1> INFO: 41600 events read in total (3399ms).
[14:00:28.770] <TB1> INFO: Test took 4268ms.
[14:00:28.774] <TB1> INFO: scanning low vcal = 90
[14:00:29.051] <TB1> INFO: Expecting 41600 events.
[14:00:33.040] <TB1> INFO: 41600 events read in total (3398ms).
[14:00:33.041] <TB1> INFO: Test took 4267ms.
[14:00:33.045] <TB1> INFO: scanning low vcal = 100
[14:00:33.321] <TB1> INFO: Expecting 41600 events.
[14:00:37.360] <TB1> INFO: 41600 events read in total (3447ms).
[14:00:37.361] <TB1> INFO: Test took 4316ms.
[14:00:37.364] <TB1> INFO: scanning low vcal = 110
[14:00:37.641] <TB1> INFO: Expecting 41600 events.
[14:00:41.659] <TB1> INFO: 41600 events read in total (3426ms).
[14:00:41.660] <TB1> INFO: Test took 4296ms.
[14:00:41.664] <TB1> INFO: scanning low vcal = 120
[14:00:41.941] <TB1> INFO: Expecting 41600 events.
[14:00:45.968] <TB1> INFO: 41600 events read in total (3435ms).
[14:00:45.968] <TB1> INFO: Test took 4304ms.
[14:00:45.971] <TB1> INFO: scanning low vcal = 130
[14:00:46.249] <TB1> INFO: Expecting 41600 events.
[14:00:50.261] <TB1> INFO: 41600 events read in total (3420ms).
[14:00:50.262] <TB1> INFO: Test took 4291ms.
[14:00:50.265] <TB1> INFO: scanning low vcal = 140
[14:00:50.542] <TB1> INFO: Expecting 41600 events.
[14:00:54.560] <TB1> INFO: 41600 events read in total (3426ms).
[14:00:54.562] <TB1> INFO: Test took 4296ms.
[14:00:54.565] <TB1> INFO: scanning low vcal = 150
[14:00:54.850] <TB1> INFO: Expecting 41600 events.
[14:00:58.871] <TB1> INFO: 41600 events read in total (3429ms).
[14:00:58.872] <TB1> INFO: Test took 4307ms.
[14:00:58.876] <TB1> INFO: scanning low vcal = 160
[14:00:59.152] <TB1> INFO: Expecting 41600 events.
[14:01:03.193] <TB1> INFO: 41600 events read in total (3449ms).
[14:01:03.194] <TB1> INFO: Test took 4318ms.
[14:01:03.197] <TB1> INFO: scanning low vcal = 170
[14:01:03.474] <TB1> INFO: Expecting 41600 events.
[14:01:07.541] <TB1> INFO: 41600 events read in total (3475ms).
[14:01:07.542] <TB1> INFO: Test took 4345ms.
[14:01:07.548] <TB1> INFO: scanning low vcal = 180
[14:01:07.823] <TB1> INFO: Expecting 41600 events.
[14:01:11.831] <TB1> INFO: 41600 events read in total (3417ms).
[14:01:11.832] <TB1> INFO: Test took 4283ms.
[14:01:11.835] <TB1> INFO: scanning low vcal = 190
[14:01:12.112] <TB1> INFO: Expecting 41600 events.
[14:01:16.140] <TB1> INFO: 41600 events read in total (3436ms).
[14:01:16.141] <TB1> INFO: Test took 4306ms.
[14:01:16.144] <TB1> INFO: scanning low vcal = 200
[14:01:16.421] <TB1> INFO: Expecting 41600 events.
[14:01:20.464] <TB1> INFO: 41600 events read in total (3451ms).
[14:01:20.465] <TB1> INFO: Test took 4321ms.
[14:01:20.469] <TB1> INFO: scanning low vcal = 210
[14:01:20.746] <TB1> INFO: Expecting 41600 events.
[14:01:24.809] <TB1> INFO: 41600 events read in total (3471ms).
[14:01:24.810] <TB1> INFO: Test took 4341ms.
[14:01:24.814] <TB1> INFO: scanning low vcal = 220
[14:01:25.090] <TB1> INFO: Expecting 41600 events.
[14:01:29.105] <TB1> INFO: 41600 events read in total (3423ms).
[14:01:29.105] <TB1> INFO: Test took 4291ms.
[14:01:29.109] <TB1> INFO: scanning low vcal = 230
[14:01:29.386] <TB1> INFO: Expecting 41600 events.
[14:01:33.393] <TB1> INFO: 41600 events read in total (3416ms).
[14:01:33.394] <TB1> INFO: Test took 4285ms.
[14:01:33.398] <TB1> INFO: scanning low vcal = 240
[14:01:33.674] <TB1> INFO: Expecting 41600 events.
[14:01:37.680] <TB1> INFO: 41600 events read in total (3414ms).
[14:01:37.682] <TB1> INFO: Test took 4284ms.
[14:01:37.685] <TB1> INFO: scanning low vcal = 250
[14:01:37.962] <TB1> INFO: Expecting 41600 events.
[14:01:41.929] <TB1> INFO: 41600 events read in total (3375ms).
[14:01:41.929] <TB1> INFO: Test took 4244ms.
[14:01:41.934] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[14:01:42.210] <TB1> INFO: Expecting 41600 events.
[14:01:46.225] <TB1> INFO: 41600 events read in total (3423ms).
[14:01:46.225] <TB1> INFO: Test took 4291ms.
[14:01:46.229] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[14:01:46.506] <TB1> INFO: Expecting 41600 events.
[14:01:50.517] <TB1> INFO: 41600 events read in total (3420ms).
[14:01:50.518] <TB1> INFO: Test took 4289ms.
[14:01:50.522] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[14:01:50.799] <TB1> INFO: Expecting 41600 events.
[14:01:54.803] <TB1> INFO: 41600 events read in total (3412ms).
[14:01:54.805] <TB1> INFO: Test took 4283ms.
[14:01:54.808] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[14:01:55.085] <TB1> INFO: Expecting 41600 events.
[14:01:59.078] <TB1> INFO: 41600 events read in total (3401ms).
[14:01:59.079] <TB1> INFO: Test took 4271ms.
[14:01:59.082] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:01:59.360] <TB1> INFO: Expecting 41600 events.
[14:02:03.367] <TB1> INFO: 41600 events read in total (3415ms).
[14:02:03.368] <TB1> INFO: Test took 4286ms.
[14:02:03.786] <TB1> INFO: PixTestGainPedestal::measure() done
[14:02:38.677] <TB1> INFO: PixTestGainPedestal::fit() done
[14:02:38.677] <TB1> INFO: non-linearity mean: 0.912 0.976 0.969 0.981 0.985 0.948 0.892 0.981 0.921 0.920 0.925 0.938 0.975 0.916 0.928 0.960
[14:02:38.677] <TB1> INFO: non-linearity RMS: 0.124 0.005 0.017 0.005 0.002 0.064 0.113 0.004 0.127 0.108 0.085 0.189 0.006 0.091 0.090 0.154
[14:02:38.677] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C0.dat
[14:02:38.692] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C1.dat
[14:02:38.704] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C2.dat
[14:02:38.717] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C3.dat
[14:02:38.731] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C4.dat
[14:02:38.744] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C5.dat
[14:02:38.757] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C6.dat
[14:02:38.771] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C7.dat
[14:02:38.784] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C8.dat
[14:02:38.797] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C9.dat
[14:02:38.810] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C10.dat
[14:02:38.825] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C11.dat
[14:02:38.844] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C12.dat
[14:02:38.863] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C13.dat
[14:02:38.882] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C14.dat
[14:02:38.896] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1011_FullQualification_2016-10-19_09h44m_1476863092//003_Fulltest_p17//phCalibrationFitErr35_C15.dat
[14:02:38.909] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[14:02:38.909] <TB1> INFO: Decoding statistics:
[14:02:38.909] <TB1> INFO: General information:
[14:02:38.909] <TB1> INFO: 16bit words read: 3269496
[14:02:38.909] <TB1> INFO: valid events total: 332800
[14:02:38.909] <TB1> INFO: empty events: 817
[14:02:38.909] <TB1> INFO: valid events with pixels: 331983
[14:02:38.909] <TB1> INFO: valid pixel hits: 636348
[14:02:38.909] <TB1> INFO: Event errors: 0
[14:02:38.909] <TB1> INFO: start marker: 0
[14:02:38.909] <TB1> INFO: stop marker: 0
[14:02:38.909] <TB1> INFO: overflow: 0
[14:02:38.909] <TB1> INFO: invalid 5bit words: 0
[14:02:38.909] <TB1> INFO: invalid XOR eye diagram: 0
[14:02:38.909] <TB1> INFO: frame (failed synchr.): 0
[14:02:38.909] <TB1> INFO: idle data (no TBM trl): 0
[14:02:38.909] <TB1> INFO: no data (only TBM hdr): 0
[14:02:38.909] <TB1> INFO: TBM errors: 0
[14:02:38.909] <TB1> INFO: flawed TBM headers: 0
[14:02:38.909] <TB1> INFO: flawed TBM trailers: 0
[14:02:38.909] <TB1> INFO: event ID mismatches: 0
[14:02:38.909] <TB1> INFO: ROC errors: 0
[14:02:38.909] <TB1> INFO: missing ROC header(s): 0
[14:02:38.909] <TB1> INFO: misplaced readback start: 0
[14:02:38.909] <TB1> INFO: Pixel decoding errors: 0
[14:02:38.909] <TB1> INFO: pixel data incomplete: 0
[14:02:38.909] <TB1> INFO: pixel address: 0
[14:02:38.909] <TB1> INFO: pulse height fill bit: 0
[14:02:38.909] <TB1> INFO: buffer corruption: 0
[14:02:38.926] <TB1> INFO: Decoding statistics:
[14:02:38.926] <TB1> INFO: General information:
[14:02:38.926] <TB1> INFO: 16bit words read: 3398904
[14:02:38.926] <TB1> INFO: valid events total: 353536
[14:02:38.926] <TB1> INFO: empty events: 19057
[14:02:38.926] <TB1> INFO: valid events with pixels: 334479
[14:02:38.926] <TB1> INFO: valid pixel hits: 638844
[14:02:38.926] <TB1> INFO: Event errors: 0
[14:02:38.926] <TB1> INFO: start marker: 0
[14:02:38.926] <TB1> INFO: stop marker: 0
[14:02:38.926] <TB1> INFO: overflow: 0
[14:02:38.926] <TB1> INFO: invalid 5bit words: 0
[14:02:38.926] <TB1> INFO: invalid XOR eye diagram: 0
[14:02:38.926] <TB1> INFO: frame (failed synchr.): 0
[14:02:38.926] <TB1> INFO: idle data (no TBM trl): 0
[14:02:38.926] <TB1> INFO: no data (only TBM hdr): 0
[14:02:38.926] <TB1> INFO: TBM errors: 0
[14:02:38.926] <TB1> INFO: flawed TBM headers: 0
[14:02:38.926] <TB1> INFO: flawed TBM trailers: 0
[14:02:38.926] <TB1> INFO: event ID mismatches: 0
[14:02:38.926] <TB1> INFO: ROC errors: 0
[14:02:38.926] <TB1> INFO: missing ROC header(s): 0
[14:02:38.926] <TB1> INFO: misplaced readback start: 0
[14:02:38.926] <TB1> INFO: Pixel decoding errors: 0
[14:02:38.926] <TB1> INFO: pixel data incomplete: 0
[14:02:38.926] <TB1> INFO: pixel address: 0
[14:02:38.926] <TB1> INFO: pulse height fill bit: 0
[14:02:38.926] <TB1> INFO: buffer corruption: 0
[14:02:38.926] <TB1> INFO: enter test to run
[14:02:38.926] <TB1> INFO: test: exit no parameter change
[14:02:39.061] <TB1> QUIET: Connection to board 154 closed.
[14:02:39.062] <TB1> INFO: pXar: this is the end, my friend