[08:41:21.418] <TB1> INFO: *** Welcome to pxar ***
[08:41:21.418] <TB1> INFO: *** Today: 2016/10/25
[08:41:21.424] <TB1> INFO: *** Version: c8ba-dirty
[08:41:21.424] <TB1> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C15.dat
[08:41:21.424] <TB1> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C1b.dat
[08:41:21.424] <TB1> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//defaultMaskFile.dat
[08:41:21.424] <TB1> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters_C15.dat
[08:41:21.480] <TB1> INFO: clk: 4
[08:41:21.480] <TB1> INFO: ctr: 4
[08:41:21.480] <TB1> INFO: sda: 19
[08:41:21.480] <TB1> INFO: tin: 9
[08:41:21.480] <TB1> INFO: level: 15
[08:41:21.480] <TB1> INFO: triggerdelay: 0
[08:41:21.480] <TB1> QUIET: Instanciating API for pxar v2.1.0+867~g2c7f7f2
[08:41:21.480] <TB1> INFO: Log level: INFO
[08:41:21.487] <TB1> INFO: Found DTB DTB_WXBYFL
[08:41:21.495] <TB1> QUIET: Connection to board DTB_WXBYFL opened.
[08:41:21.497] <TB1> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 153
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WXBYFL
MAC address: 40D855118099
Hostname: pixelDTB153
Comment:
------------------------------------------------------
[08:41:21.499] <TB1> INFO: RPC call hashes of host and DTB match: 486171790
[08:41:22.985] <TB1> INFO: DUT info:
[08:41:22.985] <TB1> INFO: The DUT currently contains the following objects:
[08:41:22.985] <TB1> INFO: 4 TBM Cores tbm10c (4 ON)
[08:41:22.985] <TB1> INFO: TBM Core alpha (0): 7 registers set
[08:41:22.985] <TB1> INFO: TBM Core beta (1): 7 registers set
[08:41:22.985] <TB1> INFO: TBM Core alpha (2): 7 registers set
[08:41:22.985] <TB1> INFO: TBM Core beta (3): 7 registers set
[08:41:22.985] <TB1> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[08:41:22.985] <TB1> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:22.985] <TB1> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[08:41:23.386] <TB1> INFO: enter 'restricted' command line mode
[08:41:23.386] <TB1> INFO: enter test to run
[08:41:23.386] <TB1> INFO: test: pretest no parameter change
[08:41:23.386] <TB1> INFO: running: pretest
[08:41:23.942] <TB1> INFO: ######################################################################
[08:41:23.942] <TB1> INFO: PixTestPretest::doTest()
[08:41:23.942] <TB1> INFO: ######################################################################
[08:41:23.943] <TB1> INFO: ----------------------------------------------------------------------
[08:41:23.943] <TB1> INFO: PixTestPretest::programROC()
[08:41:23.943] <TB1> INFO: ----------------------------------------------------------------------
[08:41:41.956] <TB1> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[08:41:41.956] <TB1> INFO: IA differences per ROC: 20.1 16.9 17.7 17.7 18.5 18.5 18.5 20.1 18.5 17.7 19.3 19.3 19.3 18.5 16.1 20.1
[08:41:41.992] <TB1> INFO: ----------------------------------------------------------------------
[08:41:41.992] <TB1> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[08:41:41.992] <TB1> INFO: ----------------------------------------------------------------------
[08:42:03.227] <TB1> INFO: PixTestPretest::setVana() done, Module Ia 387.5 mA = 24.2188 mA/ROC
[08:42:03.227] <TB1> INFO: i(loss) [mA/ROC]: 19.3 17.7 20.1 19.3 19.3 18.5 20.9 19.3 19.3 20.1 19.3 19.3 19.3 18.5 19.3 19.3
[08:42:03.255] <TB1> INFO: ----------------------------------------------------------------------
[08:42:03.255] <TB1> INFO: PixTestPretest::findTiming()
[08:42:03.255] <TB1> INFO: ----------------------------------------------------------------------
[08:42:03.255] <TB1> INFO: PixTestCmd::init()

[08:42:34.234] <TB1> INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[08:42:34.234] <TB1> INFO: (success/tries = 100/100), width = 4
[08:42:35.720] <TB1> INFO: ----------------------------------------------------------------------
[08:42:35.720] <TB1> INFO: PixTestPretest::findWorkingPixel()
[08:42:35.720] <TB1> INFO: ----------------------------------------------------------------------
[08:42:35.812] <TB1> INFO: Expecting 231680 events.
[08:42:45.575] <TB1> INFO: 231680 events read in total (9171ms).
[08:42:45.582] <TB1> INFO: Test took 9859ms.
[08:42:45.824] <TB1> INFO: Found working pixel in all ROCs: col/row = 12/22
[08:42:45.853] <TB1> INFO: ----------------------------------------------------------------------
[08:42:45.853] <TB1> INFO: PixTestPretest::setVthrCompCalDel()
[08:42:45.853] <TB1> INFO: ----------------------------------------------------------------------
[08:42:45.945] <TB1> INFO: Expecting 231680 events.
[08:42:55.670] <TB1> INFO: 231680 events read in total (9133ms).
[08:42:55.676] <TB1> INFO: Test took 9819ms.
[08:42:55.937] <TB1> INFO: PixTestPretest::setVthrCompCalDel() done
[08:42:55.937] <TB1> INFO: CalDel: 93 96 87 99 101 85 103 98 80 98 84 93 83 93 86 87
[08:42:55.937] <TB1> INFO: VthrComp: 51 51 52 52 53 52 54 51 53 51 51 51 56 54 51 51
[08:42:55.939] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C0.dat
[08:42:55.939] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C1.dat
[08:42:55.939] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C2.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C3.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C4.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C5.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C6.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C7.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C8.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C9.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C10.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C11.dat
[08:42:55.940] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C12.dat
[08:42:55.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C13.dat
[08:42:55.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C14.dat
[08:42:55.941] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters_C15.dat
[08:42:55.941] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C0a.dat
[08:42:55.941] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C0b.dat
[08:42:55.941] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C1a.dat
[08:42:55.941] <TB1> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//tbmParameters_C1b.dat
[08:42:55.941] <TB1> INFO: PixTestPretest::doTest() done, duration: 92 seconds
[08:42:56.042] <TB1> INFO: enter test to run
[08:42:56.042] <TB1> INFO: test: FullTest no parameter change
[08:42:56.042] <TB1> INFO: running: fulltest
[08:42:56.042] <TB1> INFO: ######################################################################
[08:42:56.042] <TB1> INFO: PixTestFullTest::doTest()
[08:42:56.042] <TB1> INFO: ######################################################################
[08:42:56.043] <TB1> INFO: ######################################################################
[08:42:56.043] <TB1> INFO: PixTestAlive::doTest()
[08:42:56.043] <TB1> INFO: ######################################################################
[08:42:56.045] <TB1> INFO: ----------------------------------------------------------------------
[08:42:56.045] <TB1> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:42:56.045] <TB1> INFO: ----------------------------------------------------------------------
[08:42:56.278] <TB1> INFO: Expecting 41600 events.
[08:42:59.975] <TB1> INFO: 41600 events read in total (3106ms).
[08:42:59.975] <TB1> INFO: Test took 3929ms.
[08:43:00.204] <TB1> INFO: PixTestAlive::aliveTest() done
[08:43:00.204] <TB1> INFO: number of dead pixels (per ROC): 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
[08:43:00.205] <TB1> INFO: ----------------------------------------------------------------------
[08:43:00.205] <TB1> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:43:00.205] <TB1> INFO: ----------------------------------------------------------------------
[08:43:00.454] <TB1> INFO: Expecting 41600 events.
[08:43:03.382] <TB1> INFO: 41600 events read in total (2336ms).
[08:43:03.382] <TB1> INFO: Test took 3176ms.
[08:43:03.382] <TB1> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[08:43:03.621] <TB1> INFO: PixTestAlive::maskTest() done
[08:43:03.621] <TB1> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:43:03.623] <TB1> INFO: ----------------------------------------------------------------------
[08:43:03.623] <TB1> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[08:43:03.623] <TB1> INFO: ----------------------------------------------------------------------
[08:43:03.856] <TB1> INFO: Expecting 41600 events.
[08:43:07.304] <TB1> INFO: 41600 events read in total (2856ms).
[08:43:07.304] <TB1> INFO: Test took 3680ms.
[08:43:07.531] <TB1> INFO: PixTestAlive::addressDecodingTest() done
[08:43:07.531] <TB1> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[08:43:07.531] <TB1> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[08:43:07.531] <TB1> INFO: Decoding statistics:
[08:43:07.531] <TB1> INFO: General information:
[08:43:07.531] <TB1> INFO: 16bit words read: 0
[08:43:07.531] <TB1> INFO: valid events total: 0
[08:43:07.531] <TB1> INFO: empty events: 0
[08:43:07.531] <TB1> INFO: valid events with pixels: 0
[08:43:07.531] <TB1> INFO: valid pixel hits: 0
[08:43:07.531] <TB1> INFO: Event errors: 0
[08:43:07.531] <TB1> INFO: start marker: 0
[08:43:07.531] <TB1> INFO: stop marker: 0
[08:43:07.531] <TB1> INFO: overflow: 0
[08:43:07.531] <TB1> INFO: invalid 5bit words: 0
[08:43:07.531] <TB1> INFO: invalid XOR eye diagram: 0
[08:43:07.531] <TB1> INFO: frame (failed synchr.): 0
[08:43:07.531] <TB1> INFO: idle data (no TBM trl): 0
[08:43:07.531] <TB1> INFO: no data (only TBM hdr): 0
[08:43:07.531] <TB1> INFO: TBM errors: 0
[08:43:07.531] <TB1> INFO: flawed TBM headers: 0
[08:43:07.531] <TB1> INFO: flawed TBM trailers: 0
[08:43:07.531] <TB1> INFO: event ID mismatches: 0
[08:43:07.531] <TB1> INFO: ROC errors: 0
[08:43:07.531] <TB1> INFO: missing ROC header(s): 0
[08:43:07.531] <TB1> INFO: misplaced readback start: 0
[08:43:07.531] <TB1> INFO: Pixel decoding errors: 0
[08:43:07.531] <TB1> INFO: pixel data incomplete: 0
[08:43:07.531] <TB1> INFO: pixel address: 0
[08:43:07.531] <TB1> INFO: pulse height fill bit: 0
[08:43:07.531] <TB1> INFO: buffer corruption: 0
[08:43:07.541] <TB1> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:43:07.542] <TB1> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr_C15.dat

[08:43:07.542] <TB1> INFO: ######################################################################
[08:43:07.542] <TB1> INFO: PixTestReadback::doTest()
[08:43:07.542] <TB1> INFO: ######################################################################
[08:43:07.542] <TB1> INFO: ----------------------------------------------------------------------
[08:43:07.542] <TB1> INFO: PixTestReadback::CalibrateVd()
[08:43:07.542] <TB1> INFO: ----------------------------------------------------------------------
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C1.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C2.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C3.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C4.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C5.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C6.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C7.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C8.dat
[08:43:17.503] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C9.dat
[08:43:17.504] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C10.dat
[08:43:17.504] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C11.dat
[08:43:17.504] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C12.dat
[08:43:17.504] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C13.dat
[08:43:17.504] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C14.dat
[08:43:17.504] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:43:17.531] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:43:17.531] <TB1> INFO: ----------------------------------------------------------------------
[08:43:17.532] <TB1> INFO: PixTestReadback::CalibrateVa()
[08:43:17.532] <TB1> INFO: ----------------------------------------------------------------------
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C1.dat
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C2.dat
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C3.dat
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C4.dat
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C5.dat
[08:43:27.416] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C6.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C7.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C8.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C9.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C10.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C11.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C12.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C13.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C14.dat
[08:43:27.417] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:43:27.445] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:43:27.445] <TB1> INFO: ----------------------------------------------------------------------
[08:43:27.445] <TB1> INFO: PixTestReadback::readbackVbg()
[08:43:27.445] <TB1> INFO: ----------------------------------------------------------------------
[08:43:35.083] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:43:35.083] <TB1> INFO: ----------------------------------------------------------------------
[08:43:35.083] <TB1> INFO: PixTestReadback::getCalibratedVbg()
[08:43:35.084] <TB1> INFO: ----------------------------------------------------------------------
[08:43:35.084] <TB1> INFO: Vbg will be calibrated using Vd calibration
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 155calibrated Vbg = 1.1656 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 151.6calibrated Vbg = 1.15876 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 157.6calibrated Vbg = 1.15713 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 157.3calibrated Vbg = 1.15486 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 165.1calibrated Vbg = 1.15812 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 156.1calibrated Vbg = 1.16061 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 149.4calibrated Vbg = 1.16092 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 151.5calibrated Vbg = 1.16244 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 151.3calibrated Vbg = 1.15412 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 148.3calibrated Vbg = 1.15748 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 154.7calibrated Vbg = 1.15502 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 151.4calibrated Vbg = 1.15168 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 163.3calibrated Vbg = 1.15537 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 150.4calibrated Vbg = 1.1582 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 155.4calibrated Vbg = 1.15903 :::*/*/*/*/
[08:43:35.084] <TB1> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 151.9calibrated Vbg = 1.16213 :::*/*/*/*/
[08:43:35.086] <TB1> INFO: ----------------------------------------------------------------------
[08:43:35.086] <TB1> INFO: PixTestReadback::CalibrateIa()
[08:43:35.086] <TB1> INFO: ----------------------------------------------------------------------
[08:46:15.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C0.dat
[08:46:15.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C1.dat
[08:46:15.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C2.dat
[08:46:15.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C3.dat
[08:46:15.364] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C4.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C5.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C6.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C7.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C8.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C9.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C10.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C11.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C12.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C13.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C14.dat
[08:46:15.365] <TB1> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//readbackCal_C15.dat
[08:46:15.393] <TB1> INFO: PixTestPattern:: pg_setup set to default.
[08:46:15.395] <TB1> INFO: PixTestReadback::doTest() done
[08:46:15.395] <TB1> INFO: Decoding statistics:
[08:46:15.395] <TB1> INFO: General information:
[08:46:15.395] <TB1> INFO: 16bit words read: 1536
[08:46:15.395] <TB1> INFO: valid events total: 256
[08:46:15.395] <TB1> INFO: empty events: 256
[08:46:15.395] <TB1> INFO: valid events with pixels: 0
[08:46:15.395] <TB1> INFO: valid pixel hits: 0
[08:46:15.395] <TB1> INFO: Event errors: 0
[08:46:15.395] <TB1> INFO: start marker: 0
[08:46:15.395] <TB1> INFO: stop marker: 0
[08:46:15.395] <TB1> INFO: overflow: 0
[08:46:15.395] <TB1> INFO: invalid 5bit words: 0
[08:46:15.395] <TB1> INFO: invalid XOR eye diagram: 0
[08:46:15.395] <TB1> INFO: frame (failed synchr.): 0
[08:46:15.395] <TB1> INFO: idle data (no TBM trl): 0
[08:46:15.395] <TB1> INFO: no data (only TBM hdr): 0
[08:46:15.395] <TB1> INFO: TBM errors: 0
[08:46:15.395] <TB1> INFO: flawed TBM headers: 0
[08:46:15.395] <TB1> INFO: flawed TBM trailers: 0
[08:46:15.395] <TB1> INFO: event ID mismatches: 0
[08:46:15.395] <TB1> INFO: ROC errors: 0
[08:46:15.395] <TB1> INFO: missing ROC header(s): 0
[08:46:15.395] <TB1> INFO: misplaced readback start: 0
[08:46:15.395] <TB1> INFO: Pixel decoding errors: 0
[08:46:15.395] <TB1> INFO: pixel data incomplete: 0
[08:46:15.395] <TB1> INFO: pixel address: 0
[08:46:15.395] <TB1> INFO: pulse height fill bit: 0
[08:46:15.395] <TB1> INFO: buffer corruption: 0
[08:46:15.435] <TB1> INFO: ######################################################################
[08:46:15.435] <TB1> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[08:46:15.435] <TB1> INFO: ######################################################################
[08:46:15.437] <TB1> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[08:46:15.448] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[08:46:15.448] <TB1> INFO: run 1 of 1
[08:46:15.679] <TB1> INFO: Expecting 3120000 events.
[08:46:46.754] <TB1> INFO: 677015 events read in total (30483ms).











[08:47:17.673] <TB1> INFO: 1350820 events read in total (61402ms).











[08:47:48.069] <TB1> INFO: 2020290 events read in total (91798ms).
[08:48:18.755] <TB1> INFO: 2688465 events read in total (122484ms).











[08:48:38.650] <TB1> INFO: 3120000 events read in total (142379ms).
[08:48:38.719] <TB1> INFO: Test took 143272ms.
[08:49:01.628] <TB1> INFO: PixTestBBMap::doTest() done with 1 decoding errors: , duration: 166 seconds
[08:49:01.628] <TB1> INFO: number of dead bumps (per ROC): 0 0 2 1 1 0 0 0 0 1 0 0 0 0 0 5
[08:49:01.628] <TB1> INFO: separation cut (per ROC): 105 101 118 116 105 105 126 125 106 117 107 106 111 120 108 109
[08:49:01.628] <TB1> INFO: Decoding statistics:
[08:49:01.628] <TB1> INFO: General information:
[08:49:01.628] <TB1> INFO: 16bit words read: 0
[08:49:01.628] <TB1> INFO: valid events total: 0
[08:49:01.628] <TB1> INFO: empty events: 0
[08:49:01.628] <TB1> INFO: valid events with pixels: 0
[08:49:01.628] <TB1> INFO: valid pixel hits: 0
[08:49:01.628] <TB1> INFO: Event errors: 0
[08:49:01.628] <TB1> INFO: start marker: 0
[08:49:01.628] <TB1> INFO: stop marker: 0
[08:49:01.628] <TB1> INFO: overflow: 0
[08:49:01.628] <TB1> INFO: invalid 5bit words: 0
[08:49:01.628] <TB1> INFO: invalid XOR eye diagram: 0
[08:49:01.628] <TB1> INFO: frame (failed synchr.): 0
[08:49:01.628] <TB1> INFO: idle data (no TBM trl): 0
[08:49:01.628] <TB1> INFO: no data (only TBM hdr): 0
[08:49:01.628] <TB1> INFO: TBM errors: 0
[08:49:01.628] <TB1> INFO: flawed TBM headers: 0
[08:49:01.628] <TB1> INFO: flawed TBM trailers: 0
[08:49:01.628] <TB1> INFO: event ID mismatches: 0
[08:49:01.628] <TB1> INFO: ROC errors: 0
[08:49:01.628] <TB1> INFO: missing ROC header(s): 0
[08:49:01.628] <TB1> INFO: misplaced readback start: 0
[08:49:01.628] <TB1> INFO: Pixel decoding errors: 0
[08:49:01.628] <TB1> INFO: pixel data incomplete: 0
[08:49:01.628] <TB1> INFO: pixel address: 0
[08:49:01.628] <TB1> INFO: pulse height fill bit: 0
[08:49:01.628] <TB1> INFO: buffer corruption: 0
[08:49:01.664] <TB1> INFO: ######################################################################
[08:49:01.664] <TB1> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:49:01.664] <TB1> INFO: ######################################################################
[08:49:01.664] <TB1> INFO: ----------------------------------------------------------------------
[08:49:01.664] <TB1> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[08:49:01.664] <TB1> INFO: ----------------------------------------------------------------------
[08:49:01.664] <TB1> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[08:49:01.674] <TB1> INFO: dacScan split into 1 runs with ntrig = 50
[08:49:01.674] <TB1> INFO: run 1 of 1
[08:49:01.906] <TB1> INFO: Expecting 36608000 events.
[08:49:25.963] <TB1> INFO: 700500 events read in total (23466ms).
[08:49:48.928] <TB1> INFO: 1383150 events read in total (46431ms).
[08:50:12.143] <TB1> INFO: 2067300 events read in total (69646ms).
[08:50:35.302] <TB1> INFO: 2748400 events read in total (92805ms).
[08:50:58.158] <TB1> INFO: 3430750 events read in total (115661ms).
[08:51:20.866] <TB1> INFO: 4111250 events read in total (138369ms).
[08:51:43.972] <TB1> INFO: 4793600 events read in total (161475ms).
[08:52:07.446] <TB1> INFO: 5474550 events read in total (184949ms).
[08:52:30.577] <TB1> INFO: 6157700 events read in total (208080ms).
[08:52:53.495] <TB1> INFO: 6838550 events read in total (230998ms).
[08:53:16.749] <TB1> INFO: 7519600 events read in total (254252ms).
[08:53:39.956] <TB1> INFO: 8199950 events read in total (277459ms).
[08:54:03.209] <TB1> INFO: 8879150 events read in total (300712ms).
[08:54:25.980] <TB1> INFO: 9558800 events read in total (323483ms).
[08:54:49.123] <TB1> INFO: 10238300 events read in total (346626ms).
[08:55:12.225] <TB1> INFO: 10915600 events read in total (369728ms).
[08:55:35.288] <TB1> INFO: 11594050 events read in total (392791ms).
[08:55:58.570] <TB1> INFO: 12272150 events read in total (416073ms).
[08:56:21.731] <TB1> INFO: 12949200 events read in total (439234ms).
[08:56:44.623] <TB1> INFO: 13622400 events read in total (462126ms).
[08:57:07.260] <TB1> INFO: 14296850 events read in total (484763ms).
[08:57:30.166] <TB1> INFO: 14972250 events read in total (507669ms).
[08:57:53.180] <TB1> INFO: 15646050 events read in total (530683ms).
[08:58:16.211] <TB1> INFO: 16321550 events read in total (553714ms).
[08:58:39.340] <TB1> INFO: 16994900 events read in total (576843ms).
[08:59:02.580] <TB1> INFO: 17668600 events read in total (600083ms).
[08:59:25.730] <TB1> INFO: 18340300 events read in total (623233ms).
[08:59:48.638] <TB1> INFO: 19011900 events read in total (646141ms).
[09:00:11.572] <TB1> INFO: 19681950 events read in total (669075ms).
[09:00:34.320] <TB1> INFO: 20352250 events read in total (691823ms).
[09:00:57.285] <TB1> INFO: 21022700 events read in total (714788ms).
[09:01:20.302] <TB1> INFO: 21691950 events read in total (737805ms).
[09:01:43.403] <TB1> INFO: 22360050 events read in total (760906ms).
[09:02:06.268] <TB1> INFO: 23029300 events read in total (783771ms).
[09:02:29.447] <TB1> INFO: 23699900 events read in total (806950ms).
[09:02:52.525] <TB1> INFO: 24371600 events read in total (830028ms).
[09:03:15.327] <TB1> INFO: 25041300 events read in total (852830ms).
[09:03:38.407] <TB1> INFO: 25710750 events read in total (875910ms).
[09:04:01.304] <TB1> INFO: 26379300 events read in total (898807ms).
[09:04:23.775] <TB1> INFO: 27047900 events read in total (921278ms).
[09:04:46.301] <TB1> INFO: 27716650 events read in total (943804ms).
[09:05:09.280] <TB1> INFO: 28384500 events read in total (966783ms).
[09:05:32.438] <TB1> INFO: 29050550 events read in total (989941ms).
[09:05:55.128] <TB1> INFO: 29717400 events read in total (1012631ms).
[09:06:18.075] <TB1> INFO: 30384800 events read in total (1035578ms).
[09:06:41.012] <TB1> INFO: 31051550 events read in total (1058515ms).
[09:07:03.748] <TB1> INFO: 31717600 events read in total (1081251ms).
[09:07:26.437] <TB1> INFO: 32383350 events read in total (1103940ms).
[09:07:49.269] <TB1> INFO: 33051700 events read in total (1126772ms).
[09:08:12.393] <TB1> INFO: 33720950 events read in total (1149896ms).
[09:08:35.056] <TB1> INFO: 34390850 events read in total (1172559ms).
[09:08:58.235] <TB1> INFO: 35062350 events read in total (1195738ms).
[09:09:21.060] <TB1> INFO: 35732450 events read in total (1218563ms).
[09:09:43.865] <TB1> INFO: 36412200 events read in total (1241368ms).
[09:09:50.752] <TB1> INFO: 36608000 events read in total (1248255ms).
[09:09:50.811] <TB1> INFO: Test took 1249137ms.
[09:09:51.293] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:09:52.999] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:09:54.546] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:09:56.821] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:09:59.159] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:01.517] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:03.543] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:05.500] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:07.247] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:08.727] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:10.446] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:12.473] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:14.389] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:15.949] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:17.557] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:19.023] <TB1> INFO: dumping ASCII scurve output file: SCurveData
[09:10:20.551] <TB1> INFO: PixTestScurves::scurves() done
[09:10:20.551] <TB1> INFO: Vcal mean: 119.72 125.04 132.66 129.67 125.70 127.84 129.06 133.24 127.40 125.21 119.78 114.92 134.37 137.97 124.30 123.96
[09:10:20.551] <TB1> INFO: Vcal RMS: 6.23 6.22 6.14 6.41 6.17 5.99 6.06 6.31 6.54 6.83 6.08 5.66 6.61 5.81 6.31 6.42
[09:10:20.551] <TB1> INFO: PixTestScurves::fullTest() done, duration: 1278 seconds
[09:10:20.551] <TB1> INFO: Decoding statistics:
[09:10:20.551] <TB1> INFO: General information:
[09:10:20.551] <TB1> INFO: 16bit words read: 0
[09:10:20.551] <TB1> INFO: valid events total: 0
[09:10:20.551] <TB1> INFO: empty events: 0
[09:10:20.551] <TB1> INFO: valid events with pixels: 0
[09:10:20.551] <TB1> INFO: valid pixel hits: 0
[09:10:20.551] <TB1> INFO: Event errors: 0
[09:10:20.551] <TB1> INFO: start marker: 0
[09:10:20.551] <TB1> INFO: stop marker: 0
[09:10:20.551] <TB1> INFO: overflow: 0
[09:10:20.551] <TB1> INFO: invalid 5bit words: 0
[09:10:20.551] <TB1> INFO: invalid XOR eye diagram: 0
[09:10:20.551] <TB1> INFO: frame (failed synchr.): 0
[09:10:20.551] <TB1> INFO: idle data (no TBM trl): 0
[09:10:20.551] <TB1> INFO: no data (only TBM hdr): 0
[09:10:20.551] <TB1> INFO: TBM errors: 0
[09:10:20.551] <TB1> INFO: flawed TBM headers: 0
[09:10:20.551] <TB1> INFO: flawed TBM trailers: 0
[09:10:20.551] <TB1> INFO: event ID mismatches: 0
[09:10:20.551] <TB1> INFO: ROC errors: 0
[09:10:20.551] <TB1> INFO: missing ROC header(s): 0
[09:10:20.551] <TB1> INFO: misplaced readback start: 0
[09:10:20.551] <TB1> INFO: Pixel decoding errors: 0
[09:10:20.551] <TB1> INFO: pixel data incomplete: 0
[09:10:20.551] <TB1> INFO: pixel address: 0
[09:10:20.551] <TB1> INFO: pulse height fill bit: 0
[09:10:20.551] <TB1> INFO: buffer corruption: 0
[09:10:20.615] <TB1> INFO: ######################################################################
[09:10:20.615] <TB1> INFO: PixTestTrim::doTest()
[09:10:20.615] <TB1> INFO: ######################################################################
[09:10:20.616] <TB1> INFO: ----------------------------------------------------------------------
[09:10:20.616] <TB1> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[09:10:20.616] <TB1> INFO: ----------------------------------------------------------------------
[09:10:20.656] <TB1> INFO: ---> VthrComp thr map (minimal VthrComp)
[09:10:20.656] <TB1> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[09:10:20.665] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:10:20.665] <TB1> INFO: run 1 of 1
[09:10:20.898] <TB1> INFO: Expecting 5025280 events.
[09:10:52.446] <TB1> INFO: 830536 events read in total (30953ms).
[09:11:23.013] <TB1> INFO: 1657592 events read in total (61521ms).
[09:11:53.215] <TB1> INFO: 2480184 events read in total (91722ms).
[09:12:23.818] <TB1> INFO: 3299496 events read in total (122325ms).
[09:12:53.854] <TB1> INFO: 4114168 events read in total (152361ms).
[09:13:24.342] <TB1> INFO: 4927592 events read in total (182849ms).
[09:13:28.215] <TB1> INFO: 5025280 events read in total (186722ms).
[09:13:28.254] <TB1> INFO: Test took 187588ms.
[09:13:43.298] <TB1> INFO: ROC 0 VthrComp = 123
[09:13:43.298] <TB1> INFO: ROC 1 VthrComp = 119
[09:13:43.299] <TB1> INFO: ROC 2 VthrComp = 129
[09:13:43.299] <TB1> INFO: ROC 3 VthrComp = 126
[09:13:43.300] <TB1> INFO: ROC 4 VthrComp = 124
[09:13:43.302] <TB1> INFO: ROC 5 VthrComp = 124
[09:13:43.302] <TB1> INFO: ROC 6 VthrComp = 133
[09:13:43.302] <TB1> INFO: ROC 7 VthrComp = 134
[09:13:43.302] <TB1> INFO: ROC 8 VthrComp = 129
[09:13:43.302] <TB1> INFO: ROC 9 VthrComp = 129
[09:13:43.302] <TB1> INFO: ROC 10 VthrComp = 123
[09:13:43.303] <TB1> INFO: ROC 11 VthrComp = 117
[09:13:43.303] <TB1> INFO: ROC 12 VthrComp = 132
[09:13:43.303] <TB1> INFO: ROC 13 VthrComp = 134
[09:13:43.303] <TB1> INFO: ROC 14 VthrComp = 128
[09:13:43.303] <TB1> INFO: ROC 15 VthrComp = 119
[09:13:43.540] <TB1> INFO: Expecting 41600 events.
[09:13:47.122] <TB1> INFO: 41600 events read in total (2991ms).
[09:13:47.123] <TB1> INFO: Test took 3818ms.
[09:13:47.132] <TB1> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[09:13:47.132] <TB1> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[09:13:47.142] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:13:47.142] <TB1> INFO: run 1 of 1
[09:13:47.420] <TB1> INFO: Expecting 5025280 events.
[09:14:14.328] <TB1> INFO: 593192 events read in total (26316ms).
[09:14:40.381] <TB1> INFO: 1184896 events read in total (52369ms).
[09:15:06.356] <TB1> INFO: 1776168 events read in total (78344ms).
[09:15:32.396] <TB1> INFO: 2365928 events read in total (104384ms).
[09:15:58.439] <TB1> INFO: 2953200 events read in total (130427ms).
[09:16:24.256] <TB1> INFO: 3539120 events read in total (156244ms).
[09:16:50.494] <TB1> INFO: 4123936 events read in total (182482ms).
[09:17:16.366] <TB1> INFO: 4708232 events read in total (208354ms).
[09:17:30.575] <TB1> INFO: 5025280 events read in total (222563ms).
[09:17:30.656] <TB1> INFO: Test took 223515ms.
[09:17:55.756] <TB1> INFO: roc 0 with ID = 0 has maximal Vcal 60.674 for pixel 17/75 mean/min/max = 46.4403/32.2044/60.6762
[09:17:55.756] <TB1> INFO: roc 1 with ID = 1 has maximal Vcal 62.4003 for pixel 27/14 mean/min/max = 47.3661/32.2591/62.473
[09:17:55.757] <TB1> INFO: roc 2 with ID = 2 has maximal Vcal 63.4894 for pixel 0/14 mean/min/max = 47.6858/31.8194/63.5522
[09:17:55.757] <TB1> INFO: roc 3 with ID = 3 has maximal Vcal 62.0657 for pixel 4/3 mean/min/max = 46.703/31.036/62.37
[09:17:55.758] <TB1> INFO: roc 4 with ID = 4 has maximal Vcal 62.2421 for pixel 2/10 mean/min/max = 46.9946/31.6452/62.344
[09:17:55.758] <TB1> INFO: roc 5 with ID = 5 has maximal Vcal 60.9145 for pixel 2/79 mean/min/max = 46.4231/31.7261/61.12
[09:17:55.758] <TB1> INFO: roc 6 with ID = 6 has maximal Vcal 61.727 for pixel 32/5 mean/min/max = 47.1815/32.6204/61.7425
[09:17:55.759] <TB1> INFO: roc 7 with ID = 7 has maximal Vcal 60.4778 for pixel 14/76 mean/min/max = 46.8823/33.2452/60.5193
[09:17:55.759] <TB1> INFO: roc 8 with ID = 8 has maximal Vcal 62.1481 for pixel 3/12 mean/min/max = 47.9825/33.7333/62.2316
[09:17:55.760] <TB1> INFO: roc 9 with ID = 9 has maximal Vcal 60.8559 for pixel 9/4 mean/min/max = 46.3224/31.7511/60.8936
[09:17:55.760] <TB1> INFO: roc 10 with ID = 10 has maximal Vcal 59.6927 for pixel 8/18 mean/min/max = 46.2114/32.6763/59.7465
[09:17:55.760] <TB1> INFO: roc 11 with ID = 11 has maximal Vcal 58.1827 for pixel 12/2 mean/min/max = 45.2883/32.3005/58.2762
[09:17:55.761] <TB1> INFO: roc 12 with ID = 12 has maximal Vcal 64.5843 for pixel 19/18 mean/min/max = 48.787/32.7228/64.8511
[09:17:55.761] <TB1> INFO: roc 13 with ID = 13 has maximal Vcal 64.3911 for pixel 22/0 mean/min/max = 48.9862/33.4961/64.4764
[09:17:55.762] <TB1> INFO: roc 14 with ID = 14 has maximal Vcal 59.6984 for pixel 10/2 mean/min/max = 45.5033/31.2785/59.7282
[09:17:55.762] <TB1> INFO: roc 15 with ID = 15 has maximal Vcal 62.8683 for pixel 10/7 mean/min/max = 47.4456/32.0172/62.874
[09:17:55.762] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:17:55.851] <TB1> INFO: Expecting 411648 events.
[09:18:05.285] <TB1> INFO: 411648 events read in total (8842ms).
[09:18:05.291] <TB1> INFO: Expecting 411648 events.
[09:18:14.575] <TB1> INFO: 411648 events read in total (8881ms).
[09:18:14.584] <TB1> INFO: Expecting 411648 events.
[09:18:23.845] <TB1> INFO: 411648 events read in total (8858ms).
[09:18:23.856] <TB1> INFO: Expecting 411648 events.
[09:18:33.133] <TB1> INFO: 411648 events read in total (8874ms).
[09:18:33.154] <TB1> INFO: Expecting 411648 events.
[09:18:42.416] <TB1> INFO: 411648 events read in total (8859ms).
[09:18:42.433] <TB1> INFO: Expecting 411648 events.
[09:18:51.747] <TB1> INFO: 411648 events read in total (8911ms).
[09:18:51.766] <TB1> INFO: Expecting 411648 events.
[09:19:01.053] <TB1> INFO: 411648 events read in total (8884ms).
[09:19:01.075] <TB1> INFO: Expecting 411648 events.
[09:19:10.345] <TB1> INFO: 411648 events read in total (8867ms).
[09:19:10.368] <TB1> INFO: Expecting 411648 events.
[09:19:19.651] <TB1> INFO: 411648 events read in total (8880ms).
[09:19:19.677] <TB1> INFO: Expecting 411648 events.
[09:19:28.948] <TB1> INFO: 411648 events read in total (8868ms).
[09:19:28.989] <TB1> INFO: Expecting 411648 events.
[09:19:38.220] <TB1> INFO: 411648 events read in total (8828ms).
[09:19:38.251] <TB1> INFO: Expecting 411648 events.
[09:19:47.535] <TB1> INFO: 411648 events read in total (8881ms).
[09:19:47.570] <TB1> INFO: Expecting 411648 events.
[09:19:56.850] <TB1> INFO: 411648 events read in total (8877ms).
[09:19:56.893] <TB1> INFO: Expecting 411648 events.
[09:20:06.181] <TB1> INFO: 411648 events read in total (8886ms).
[09:20:06.222] <TB1> INFO: Expecting 411648 events.
[09:20:15.471] <TB1> INFO: 411648 events read in total (8846ms).
[09:20:15.512] <TB1> INFO: Expecting 411648 events.
[09:20:24.748] <TB1> INFO: 411648 events read in total (8833ms).
[09:20:24.817] <TB1> INFO: Test took 149055ms.
[09:20:25.428] <TB1> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[09:20:25.438] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:20:25.438] <TB1> INFO: run 1 of 1
[09:20:25.671] <TB1> INFO: Expecting 5025280 events.
[09:20:52.152] <TB1> INFO: 587696 events read in total (25889ms).
[09:21:18.046] <TB1> INFO: 1174304 events read in total (51783ms).
[09:21:43.930] <TB1> INFO: 1759744 events read in total (77667ms).
[09:22:10.276] <TB1> INFO: 2346640 events read in total (104013ms).
[09:22:36.434] <TB1> INFO: 2936680 events read in total (130172ms).
[09:23:02.565] <TB1> INFO: 3526272 events read in total (156302ms).
[09:23:28.507] <TB1> INFO: 4114352 events read in total (182244ms).
[09:23:54.462] <TB1> INFO: 4705704 events read in total (208199ms).
[09:24:08.992] <TB1> INFO: 5025280 events read in total (222729ms).
[09:24:09.140] <TB1> INFO: Test took 223701ms.
[09:24:32.358] <TB1> INFO: ---> TrimStepCorr4 extremal thresholds: 3.689161 .. 143.474899
[09:24:32.652] <TB1> INFO: Expecting 208000 events.
[09:24:42.410] <TB1> INFO: 208000 events read in total (9167ms).
[09:24:42.411] <TB1> INFO: Test took 10052ms.
[09:24:42.458] <TB1> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 3 .. 153 (-1/-1) hits flags = 528 (plus default)
[09:24:42.468] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:24:42.468] <TB1> INFO: run 1 of 1
[09:24:42.746] <TB1> INFO: Expecting 5025280 events.
[09:25:09.735] <TB1> INFO: 583192 events read in total (26397ms).
[09:25:35.820] <TB1> INFO: 1166560 events read in total (52483ms).
[09:26:02.507] <TB1> INFO: 1750144 events read in total (79169ms).
[09:26:28.694] <TB1> INFO: 2333688 events read in total (105357ms).
[09:26:54.831] <TB1> INFO: 2916848 events read in total (131493ms).
[09:27:21.475] <TB1> INFO: 3498824 events read in total (158137ms).
[09:27:47.452] <TB1> INFO: 4080376 events read in total (184114ms).
[09:28:13.350] <TB1> INFO: 4661816 events read in total (210012ms).
[09:28:29.583] <TB1> INFO: 5025280 events read in total (226245ms).
[09:28:29.707] <TB1> INFO: Test took 227239ms.
[09:28:55.276] <TB1> INFO: ---> TrimStepCorr2 extremal thresholds: 27.149233 .. 47.060421
[09:28:55.510] <TB1> INFO: Expecting 208000 events.
[09:29:05.182] <TB1> INFO: 208000 events read in total (9080ms).
[09:29:05.183] <TB1> INFO: Test took 9906ms.
[09:29:05.229] <TB1> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 17 .. 57 (-1/-1) hits flags = 528 (plus default)
[09:29:05.239] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:29:05.239] <TB1> INFO: run 1 of 1
[09:29:05.519] <TB1> INFO: Expecting 1364480 events.
[09:29:34.066] <TB1> INFO: 653040 events read in total (27955ms).
[09:30:02.097] <TB1> INFO: 1304336 events read in total (55986ms).
[09:30:05.038] <TB1> INFO: 1364480 events read in total (58927ms).
[09:30:05.067] <TB1> INFO: Test took 59828ms.
[09:30:17.104] <TB1> INFO: ---> TrimStepCorr1a extremal thresholds: 28.057342 .. 48.511101
[09:30:17.345] <TB1> INFO: Expecting 208000 events.
[09:30:27.288] <TB1> INFO: 208000 events read in total (9352ms).
[09:30:27.289] <TB1> INFO: Test took 10183ms.
[09:30:27.335] <TB1> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 18 .. 58 (-1/-1) hits flags = 528 (plus default)
[09:30:27.345] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:30:27.345] <TB1> INFO: run 1 of 1
[09:30:27.623] <TB1> INFO: Expecting 1364480 events.
[09:30:55.972] <TB1> INFO: 645168 events read in total (27758ms).
[09:31:23.770] <TB1> INFO: 1289104 events read in total (55556ms).
[09:31:27.357] <TB1> INFO: 1364480 events read in total (59143ms).
[09:31:27.380] <TB1> INFO: Test took 60036ms.
[09:31:39.661] <TB1> INFO: ---> TrimStepCorr1b extremal thresholds: 26.887737 .. 50.007436
[09:31:39.896] <TB1> INFO: Expecting 208000 events.
[09:31:50.120] <TB1> INFO: 208000 events read in total (9633ms).
[09:31:50.121] <TB1> INFO: Test took 10459ms.
[09:31:50.193] <TB1> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 16 .. 60 (-1/-1) hits flags = 528 (plus default)
[09:31:50.205] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:31:50.205] <TB1> INFO: run 1 of 1
[09:31:50.483] <TB1> INFO: Expecting 1497600 events.
[09:32:19.008] <TB1> INFO: 646760 events read in total (27934ms).
[09:32:46.675] <TB1> INFO: 1292128 events read in total (55602ms).
[09:32:55.422] <TB1> INFO: 1497600 events read in total (64348ms).
[09:32:55.450] <TB1> INFO: Test took 65246ms.
[09:33:08.489] <TB1> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[09:33:08.489] <TB1> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[09:33:08.500] <TB1> INFO: dacScan split into 1 runs with ntrig = 8
[09:33:08.500] <TB1> INFO: run 1 of 1
[09:33:08.756] <TB1> INFO: Expecting 1364480 events.
[09:33:37.647] <TB1> INFO: 668408 events read in total (28299ms).
[09:34:06.077] <TB1> INFO: 1336280 events read in total (56729ms).
[09:34:07.674] <TB1> INFO: 1364480 events read in total (58326ms).
[09:34:07.696] <TB1> INFO: Test took 59195ms.
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C0.dat
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C1.dat
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C2.dat
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C3.dat
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C4.dat
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C5.dat
[09:34:19.928] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C6.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C7.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C8.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C9.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C10.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C11.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C12.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C13.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C14.dat
[09:34:19.929] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C15.dat
[09:34:19.929] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C0.dat
[09:34:19.936] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C1.dat
[09:34:19.944] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C2.dat
[09:34:19.952] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C3.dat
[09:34:19.960] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C4.dat
[09:34:19.968] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C5.dat
[09:34:19.977] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C6.dat
[09:34:19.986] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C7.dat
[09:34:19.994] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C8.dat
[09:34:19.003] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C9.dat
[09:34:20.010] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C10.dat
[09:34:20.016] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C11.dat
[09:34:20.022] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C12.dat
[09:34:20.027] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C13.dat
[09:34:20.033] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C14.dat
[09:34:20.038] <TB1> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//trimParameters35_C15.dat
[09:34:20.044] <TB1> INFO: PixTestTrim::trimTest() done
[09:34:20.044] <TB1> INFO: vtrim: 128 136 163 129 136 120 155 120 141 156 128 131 147 147 145 151
[09:34:20.044] <TB1> INFO: vthrcomp: 123 119 129 126 124 124 133 134 129 129 123 117 132 134 128 119
[09:34:20.044] <TB1> INFO: vcal mean: 34.98 35.68 35.44 35.26 35.43 35.05 35.08 35.04 35.09 34.96 34.97 34.95 35.47 35.61 34.95 35.13
[09:34:20.044] <TB1> INFO: vcal RMS: 1.04 1.97 1.68 1.65 1.57 1.17 1.26 1.01 1.18 1.09 1.09 1.02 1.59 1.79 1.22 1.41
[09:34:20.044] <TB1> INFO: bits mean: 9.65 10.24 10.35 9.80 10.00 9.53 9.74 9.01 9.21 10.07 9.65 10.03 9.52 9.91 10.50 10.09
[09:34:20.044] <TB1> INFO: bits RMS: 2.52 2.40 2.33 2.72 2.59 2.75 2.48 2.72 2.47 2.43 2.53 2.45 2.53 2.30 2.32 2.39
[09:34:20.052] <TB1> INFO: ----------------------------------------------------------------------
[09:34:20.052] <TB1> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[09:34:20.052] <TB1> INFO: ----------------------------------------------------------------------
[09:34:20.055] <TB1> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[09:34:20.067] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:34:20.067] <TB1> INFO: run 1 of 1
[09:34:20.358] <TB1> INFO: Expecting 4160000 events.
[09:34:53.519] <TB1> INFO: 773205 events read in total (32569ms).
[09:35:26.160] <TB1> INFO: 1538775 events read in total (65210ms).
[09:35:58.446] <TB1> INFO: 2296135 events read in total (97496ms).
[09:36:30.596] <TB1> INFO: 3050155 events read in total (129646ms).
[09:37:02.369] <TB1> INFO: 3800525 events read in total (161419ms).
[09:37:17.894] <TB1> INFO: 4160000 events read in total (176944ms).
[09:37:17.939] <TB1> INFO: Test took 177872ms.
[09:37:40.996] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[09:37:40.005] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:37:40.005] <TB1> INFO: run 1 of 1
[09:37:41.239] <TB1> INFO: Expecting 4347200 events.
[09:38:13.783] <TB1> INFO: 734160 events read in total (31952ms).
[09:38:45.443] <TB1> INFO: 1463405 events read in total (63612ms).
[09:39:17.138] <TB1> INFO: 2187060 events read in total (95307ms).
[09:39:48.361] <TB1> INFO: 2906065 events read in total (126530ms).
[09:40:19.999] <TB1> INFO: 3622865 events read in total (158168ms).
[09:40:51.528] <TB1> INFO: 4341895 events read in total (189697ms).
[09:40:52.160] <TB1> INFO: 4347200 events read in total (190329ms).
[09:40:52.228] <TB1> INFO: Test took 191222ms.
[09:41:21.337] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 208 (-1/-1) hits flags = 528 (plus default)
[09:41:21.349] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:41:21.349] <TB1> INFO: run 1 of 1
[09:41:21.675] <TB1> INFO: Expecting 4347200 events.
[09:41:53.720] <TB1> INFO: 734385 events read in total (31454ms).
[09:42:25.361] <TB1> INFO: 1463930 events read in total (63095ms).
[09:42:56.757] <TB1> INFO: 2188060 events read in total (94491ms).
[09:43:28.104] <TB1> INFO: 2907500 events read in total (125838ms).
[09:43:59.143] <TB1> INFO: 3624645 events read in total (156877ms).
[09:44:30.532] <TB1> INFO: 4344040 events read in total (188266ms).
[09:44:31.086] <TB1> INFO: 4347200 events read in total (188820ms).
[09:44:31.148] <TB1> INFO: Test took 189799ms.
[09:44:56.516] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 205 (-1/-1) hits flags = 528 (plus default)
[09:44:56.526] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:44:56.526] <TB1> INFO: run 1 of 1
[09:44:56.758] <TB1> INFO: Expecting 4284800 events.
[09:45:29.007] <TB1> INFO: 738390 events read in total (31657ms).
[09:46:00.305] <TB1> INFO: 1471660 events read in total (62955ms).
[09:46:31.872] <TB1> INFO: 2198835 events read in total (94522ms).
[09:47:03.375] <TB1> INFO: 2921980 events read in total (126025ms).
[09:47:34.594] <TB1> INFO: 3642055 events read in total (157244ms).
[09:48:02.637] <TB1> INFO: 4284800 events read in total (185287ms).
[09:48:02.705] <TB1> INFO: Test took 186179ms.
[09:48:29.724] <TB1> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 209 (-1/-1) hits flags = 528 (plus default)
[09:48:29.734] <TB1> INFO: dacScan split into 1 runs with ntrig = 5
[09:48:29.734] <TB1> INFO: run 1 of 1
[09:48:29.966] <TB1> INFO: Expecting 4368000 events.
[09:49:01.951] <TB1> INFO: 732900 events read in total (31393ms).
[09:49:33.160] <TB1> INFO: 1461295 events read in total (62602ms).
[09:50:04.828] <TB1> INFO: 2183980 events read in total (94270ms).
[09:50:36.218] <TB1> INFO: 2902045 events read in total (125660ms).
[09:51:07.601] <TB1> INFO: 3618100 events read in total (157043ms).
[09:51:38.003] <TB1> INFO: 4335395 events read in total (188445ms).
[09:51:40.786] <TB1> INFO: 4368000 events read in total (190228ms).
[09:51:40.840] <TB1> INFO: Test took 191106ms.
[09:52:08.261] <TB1> INFO: PixTestTrim::trimBitTest() done
[09:52:08.262] <TB1> INFO: PixTestTrim::doTest() done, duration: 2507 seconds
[09:52:08.262] <TB1> INFO: Decoding statistics:
[09:52:08.262] <TB1> INFO: General information:
[09:52:08.262] <TB1> INFO: 16bit words read: 0
[09:52:08.262] <TB1> INFO: valid events total: 0
[09:52:08.262] <TB1> INFO: empty events: 0
[09:52:08.262] <TB1> INFO: valid events with pixels: 0
[09:52:08.262] <TB1> INFO: valid pixel hits: 0
[09:52:08.262] <TB1> INFO: Event errors: 0
[09:52:08.262] <TB1> INFO: start marker: 0
[09:52:08.262] <TB1> INFO: stop marker: 0
[09:52:08.262] <TB1> INFO: overflow: 0
[09:52:08.262] <TB1> INFO: invalid 5bit words: 0
[09:52:08.262] <TB1> INFO: invalid XOR eye diagram: 0
[09:52:08.262] <TB1> INFO: frame (failed synchr.): 0
[09:52:08.262] <TB1> INFO: idle data (no TBM trl): 0
[09:52:08.262] <TB1> INFO: no data (only TBM hdr): 0
[09:52:08.262] <TB1> INFO: TBM errors: 0
[09:52:08.262] <TB1> INFO: flawed TBM headers: 0
[09:52:08.262] <TB1> INFO: flawed TBM trailers: 0
[09:52:08.262] <TB1> INFO: event ID mismatches: 0
[09:52:08.262] <TB1> INFO: ROC errors: 0
[09:52:08.262] <TB1> INFO: missing ROC header(s): 0
[09:52:08.262] <TB1> INFO: misplaced readback start: 0
[09:52:08.262] <TB1> INFO: Pixel decoding errors: 0
[09:52:08.262] <TB1> INFO: pixel data incomplete: 0
[09:52:08.262] <TB1> INFO: pixel address: 0
[09:52:08.262] <TB1> INFO: pulse height fill bit: 0
[09:52:08.262] <TB1> INFO: buffer corruption: 0
[09:52:08.961] <TB1> INFO: ######################################################################
[09:52:08.961] <TB1> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[09:52:08.961] <TB1> INFO: ######################################################################
[09:52:09.195] <TB1> INFO: Expecting 41600 events.
[09:52:12.663] <TB1> INFO: 41600 events read in total (2876ms).
[09:52:12.664] <TB1> INFO: Test took 3702ms.
[09:52:13.134] <TB1> INFO: Expecting 41600 events.
[09:52:16.656] <TB1> INFO: 41600 events read in total (2931ms).
[09:52:16.657] <TB1> INFO: Test took 3787ms.
[09:52:16.972] <TB1> INFO: Expecting 41600 events.
[09:52:20.687] <TB1> INFO: 41600 events read in total (3124ms).
[09:52:20.688] <TB1> INFO: Test took 4004ms.
[09:52:20.976] <TB1> INFO: Expecting 41600 events.
[09:52:24.554] <TB1> INFO: 41600 events read in total (2986ms).
[09:52:24.554] <TB1> INFO: Test took 3843ms.
[09:52:24.842] <TB1> INFO: Expecting 41600 events.
[09:52:28.542] <TB1> INFO: 41600 events read in total (3108ms).
[09:52:28.543] <TB1> INFO: Test took 3965ms.
[09:52:28.831] <TB1> INFO: Expecting 41600 events.
[09:52:32.421] <TB1> INFO: 41600 events read in total (2998ms).
[09:52:32.422] <TB1> INFO: Test took 3856ms.
[09:52:32.710] <TB1> INFO: Expecting 41600 events.
[09:52:36.175] <TB1> INFO: 41600 events read in total (2873ms).
[09:52:36.176] <TB1> INFO: Test took 3730ms.
[09:52:36.464] <TB1> INFO: Expecting 41600 events.
[09:52:40.166] <TB1> INFO: 41600 events read in total (3110ms).
[09:52:40.167] <TB1> INFO: Test took 3967ms.
[09:52:40.460] <TB1> INFO: Expecting 41600 events.
[09:52:44.051] <TB1> INFO: 41600 events read in total (3000ms).
[09:52:44.052] <TB1> INFO: Test took 3857ms.
[09:52:44.343] <TB1> INFO: Expecting 41600 events.
[09:52:47.885] <TB1> INFO: 41600 events read in total (2950ms).
[09:52:47.886] <TB1> INFO: Test took 3808ms.
[09:52:48.196] <TB1> INFO: Expecting 41600 events.
[09:52:51.801] <TB1> INFO: 41600 events read in total (3014ms).
[09:52:51.802] <TB1> INFO: Test took 3890ms.
[09:52:52.090] <TB1> INFO: Expecting 41600 events.
[09:52:55.614] <TB1> INFO: 41600 events read in total (2933ms).
[09:52:55.615] <TB1> INFO: Test took 3790ms.
[09:52:55.931] <TB1> INFO: Expecting 41600 events.
[09:52:59.514] <TB1> INFO: 41600 events read in total (2991ms).
[09:52:59.514] <TB1> INFO: Test took 3871ms.
[09:52:59.803] <TB1> INFO: Expecting 41600 events.
[09:53:03.273] <TB1> INFO: 41600 events read in total (2879ms).
[09:53:03.274] <TB1> INFO: Test took 3736ms.
[09:53:03.585] <TB1> INFO: Expecting 41600 events.
[09:53:07.220] <TB1> INFO: 41600 events read in total (3043ms).
[09:53:07.221] <TB1> INFO: Test took 3923ms.
[09:53:07.513] <TB1> INFO: Expecting 41600 events.
[09:53:11.097] <TB1> INFO: 41600 events read in total (2993ms).
[09:53:11.097] <TB1> INFO: Test took 3849ms.
[09:53:11.403] <TB1> INFO: Expecting 41600 events.
[09:53:14.001] <TB1> INFO: 41600 events read in total (3006ms).
[09:53:14.002] <TB1> INFO: Test took 3881ms.
[09:53:15.293] <TB1> INFO: Expecting 41600 events.
[09:53:18.809] <TB1> INFO: 41600 events read in total (2924ms).
[09:53:18.809] <TB1> INFO: Test took 3780ms.
[09:53:19.101] <TB1> INFO: Expecting 41600 events.
[09:53:22.734] <TB1> INFO: 41600 events read in total (3042ms).
[09:53:22.735] <TB1> INFO: Test took 3899ms.
[09:53:23.022] <TB1> INFO: Expecting 41600 events.
[09:53:26.718] <TB1> INFO: 41600 events read in total (3104ms).
[09:53:26.719] <TB1> INFO: Test took 3961ms.
[09:53:27.034] <TB1> INFO: Expecting 41600 events.
[09:53:30.799] <TB1> INFO: 41600 events read in total (3173ms).
[09:53:30.799] <TB1> INFO: Test took 4057ms.
[09:53:31.090] <TB1> INFO: Expecting 41600 events.
[09:53:34.711] <TB1> INFO: 41600 events read in total (3029ms).
[09:53:34.712] <TB1> INFO: Test took 3886ms.
[09:53:35.020] <TB1> INFO: Expecting 41600 events.
[09:53:38.728] <TB1> INFO: 41600 events read in total (3110ms).
[09:53:38.729] <TB1> INFO: Test took 3993ms.
[09:53:39.043] <TB1> INFO: Expecting 41600 events.
[09:53:42.665] <TB1> INFO: 41600 events read in total (3030ms).
[09:53:42.666] <TB1> INFO: Test took 3913ms.
[09:53:42.957] <TB1> INFO: Expecting 41600 events.
[09:53:46.553] <TB1> INFO: 41600 events read in total (3004ms).
[09:53:46.554] <TB1> INFO: Test took 3862ms.
[09:53:46.842] <TB1> INFO: Expecting 41600 events.
[09:53:50.534] <TB1> INFO: 41600 events read in total (3101ms).
[09:53:50.535] <TB1> INFO: Test took 3958ms.
[09:53:50.823] <TB1> INFO: Expecting 41600 events.
[09:53:54.561] <TB1> INFO: 41600 events read in total (3147ms).
[09:53:54.562] <TB1> INFO: Test took 4004ms.
[09:53:54.851] <TB1> INFO: Expecting 41600 events.
[09:53:58.427] <TB1> INFO: 41600 events read in total (2984ms).
[09:53:58.428] <TB1> INFO: Test took 3842ms.
[09:53:58.720] <TB1> INFO: Expecting 2560 events.
[09:53:59.604] <TB1> INFO: 2560 events read in total (292ms).
[09:53:59.604] <TB1> INFO: Test took 1160ms.
[09:53:59.912] <TB1> INFO: Expecting 2560 events.
[09:54:00.797] <TB1> INFO: 2560 events read in total (293ms).
[09:54:00.797] <TB1> INFO: Test took 1192ms.
[09:54:01.105] <TB1> INFO: Expecting 2560 events.
[09:54:01.989] <TB1> INFO: 2560 events read in total (293ms).
[09:54:01.989] <TB1> INFO: Test took 1192ms.
[09:54:02.297] <TB1> INFO: Expecting 2560 events.
[09:54:03.180] <TB1> INFO: 2560 events read in total (291ms).
[09:54:03.180] <TB1> INFO: Test took 1191ms.
[09:54:03.488] <TB1> INFO: Expecting 2560 events.
[09:54:04.369] <TB1> INFO: 2560 events read in total (289ms).
[09:54:04.369] <TB1> INFO: Test took 1188ms.
[09:54:04.677] <TB1> INFO: Expecting 2560 events.
[09:54:05.557] <TB1> INFO: 2560 events read in total (288ms).
[09:54:05.557] <TB1> INFO: Test took 1188ms.
[09:54:05.864] <TB1> INFO: Expecting 2560 events.
[09:54:06.747] <TB1> INFO: 2560 events read in total (291ms).
[09:54:06.747] <TB1> INFO: Test took 1190ms.
[09:54:07.055] <TB1> INFO: Expecting 2560 events.
[09:54:07.935] <TB1> INFO: 2560 events read in total (288ms).
[09:54:07.935] <TB1> INFO: Test took 1188ms.
[09:54:08.243] <TB1> INFO: Expecting 2560 events.
[09:54:09.126] <TB1> INFO: 2560 events read in total (291ms).
[09:54:09.126] <TB1> INFO: Test took 1190ms.
[09:54:09.434] <TB1> INFO: Expecting 2560 events.
[09:54:10.314] <TB1> INFO: 2560 events read in total (288ms).
[09:54:10.314] <TB1> INFO: Test took 1187ms.
[09:54:10.622] <TB1> INFO: Expecting 2560 events.
[09:54:11.501] <TB1> INFO: 2560 events read in total (288ms).
[09:54:11.501] <TB1> INFO: Test took 1186ms.
[09:54:11.809] <TB1> INFO: Expecting 2560 events.
[09:54:12.688] <TB1> INFO: 2560 events read in total (287ms).
[09:54:12.688] <TB1> INFO: Test took 1186ms.
[09:54:12.997] <TB1> INFO: Expecting 2560 events.
[09:54:13.885] <TB1> INFO: 2560 events read in total (297ms).
[09:54:13.885] <TB1> INFO: Test took 1196ms.
[09:54:14.193] <TB1> INFO: Expecting 2560 events.
[09:54:15.077] <TB1> INFO: 2560 events read in total (292ms).
[09:54:15.077] <TB1> INFO: Test took 1192ms.
[09:54:15.385] <TB1> INFO: Expecting 2560 events.
[09:54:16.269] <TB1> INFO: 2560 events read in total (293ms).
[09:54:16.269] <TB1> INFO: Test took 1191ms.
[09:54:16.577] <TB1> INFO: Expecting 2560 events.
[09:54:17.461] <TB1> INFO: 2560 events read in total (292ms).
[09:54:17.461] <TB1> INFO: Test took 1192ms.
[09:54:17.464] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:54:17.770] <TB1> INFO: Expecting 655360 events.
[09:54:32.462] <TB1> INFO: 655360 events read in total (14100ms).
[09:54:32.472] <TB1> INFO: Expecting 655360 events.
[09:54:46.990] <TB1> INFO: 655360 events read in total (14115ms).
[09:54:47.012] <TB1> INFO: Expecting 655360 events.
[09:55:01.381] <TB1> INFO: 655360 events read in total (13966ms).
[09:55:01.400] <TB1> INFO: Expecting 655360 events.
[09:55:15.992] <TB1> INFO: 655360 events read in total (14190ms).
[09:55:16.014] <TB1> INFO: Expecting 655360 events.
[09:55:30.495] <TB1> INFO: 655360 events read in total (14078ms).
[09:55:30.533] <TB1> INFO: Expecting 655360 events.
[09:55:44.924] <TB1> INFO: 655360 events read in total (13988ms).
[09:55:44.954] <TB1> INFO: Expecting 655360 events.
[09:55:59.427] <TB1> INFO: 655360 events read in total (14070ms).
[09:55:59.461] <TB1> INFO: Expecting 655360 events.
[09:56:14.078] <TB1> INFO: 655360 events read in total (14213ms).
[09:56:14.135] <TB1> INFO: Expecting 655360 events.
[09:56:28.711] <TB1> INFO: 655360 events read in total (14173ms).
[09:56:28.777] <TB1> INFO: Expecting 655360 events.
[09:56:43.211] <TB1> INFO: 655360 events read in total (14031ms).
[09:56:43.277] <TB1> INFO: Expecting 655360 events.
[09:56:57.664] <TB1> INFO: 655360 events read in total (13984ms).
[09:56:57.717] <TB1> INFO: Expecting 655360 events.
[09:57:12.246] <TB1> INFO: 655360 events read in total (14126ms).
[09:57:12.330] <TB1> INFO: Expecting 655360 events.
[09:57:26.909] <TB1> INFO: 655360 events read in total (14176ms).
[09:57:26.970] <TB1> INFO: Expecting 655360 events.
[09:57:41.423] <TB1> INFO: 655360 events read in total (14050ms).
[09:57:41.488] <TB1> INFO: Expecting 655360 events.
[09:57:56.050] <TB1> INFO: 655360 events read in total (14159ms).
[09:57:56.121] <TB1> INFO: Expecting 655360 events.
[09:58:10.747] <TB1> INFO: 655360 events read in total (14223ms).
[09:58:10.822] <TB1> INFO: Test took 233358ms.
[09:58:10.900] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[09:58:11.165] <TB1> INFO: Expecting 655360 events.
[09:58:25.837] <TB1> INFO: 655360 events read in total (14074ms).
[09:58:25.847] <TB1> INFO: Expecting 655360 events.
[09:58:40.039] <TB1> INFO: 655360 events read in total (13789ms).
[09:58:40.053] <TB1> INFO: Expecting 655360 events.
[09:58:54.389] <TB1> INFO: 655360 events read in total (13933ms).
[09:58:54.407] <TB1> INFO: Expecting 655360 events.
[09:59:08.565] <TB1> INFO: 655360 events read in total (13755ms).
[09:59:08.587] <TB1> INFO: Expecting 655360 events.
[09:59:22.712] <TB1> INFO: 655360 events read in total (13722ms).
[09:59:22.750] <TB1> INFO: Expecting 655360 events.
[09:59:36.001] <TB1> INFO: 655360 events read in total (13848ms).
[09:59:37.030] <TB1> INFO: Expecting 655360 events.
[09:59:51.426] <TB1> INFO: 655360 events read in total (13993ms).
[09:59:51.461] <TB1> INFO: Expecting 655360 events.
[10:00:05.779] <TB1> INFO: 655360 events read in total (13915ms).
[10:00:05.835] <TB1> INFO: Expecting 655360 events.
[10:00:20.038] <TB1> INFO: 655360 events read in total (13800ms).
[10:00:20.079] <TB1> INFO: Expecting 655360 events.
[10:00:34.342] <TB1> INFO: 655360 events read in total (13860ms).
[10:00:34.410] <TB1> INFO: Expecting 655360 events.
[10:00:48.777] <TB1> INFO: 655360 events read in total (13964ms).
[10:00:48.854] <TB1> INFO: Expecting 655360 events.
[10:01:03.113] <TB1> INFO: 655360 events read in total (13856ms).
[10:01:03.171] <TB1> INFO: Expecting 655360 events.
[10:01:17.517] <TB1> INFO: 655360 events read in total (13943ms).
[10:01:17.579] <TB1> INFO: Expecting 655360 events.
[10:01:31.912] <TB1> INFO: 655360 events read in total (13930ms).
[10:01:31.977] <TB1> INFO: Expecting 655360 events.
[10:01:46.598] <TB1> INFO: 655360 events read in total (14218ms).
[10:01:46.700] <TB1> INFO: Expecting 655360 events.
[10:02:01.046] <TB1> INFO: 655360 events read in total (13943ms).
[10:02:01.153] <TB1> INFO: Test took 230253ms.
[10:02:01.312] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.317] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.322] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.327] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.331] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.336] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.340] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[10:02:01.345] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[10:02:01.350] <TB1> INFO: safety margin for low PH: adding 3, margin is now 23
[10:02:01.354] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.359] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.364] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.368] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[10:02:01.373] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[10:02:01.378] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.382] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.388] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.392] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.397] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.401] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.406] <TB1> INFO: safety margin for low PH: adding 1, margin is now 21
[10:02:01.411] <TB1> INFO: safety margin for low PH: adding 2, margin is now 22
[10:02:01.415] <TB1> INFO: safety margin for low PH: adding 0, margin is now 20
[10:02:01.448] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C0.dat
[10:02:01.448] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C1.dat
[10:02:01.448] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C2.dat
[10:02:01.448] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C3.dat
[10:02:01.448] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C4.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C5.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C6.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C7.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C8.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C9.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C10.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C11.dat
[10:02:01.449] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C12.dat
[10:02:01.450] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C13.dat
[10:02:01.450] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C14.dat
[10:02:01.450] <TB1> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//dacParameters35_C15.dat
[10:02:01.684] <TB1> INFO: Expecting 41600 events.
[10:02:04.785] <TB1> INFO: 41600 events read in total (2509ms).
[10:02:04.786] <TB1> INFO: Test took 3333ms.
[10:02:05.267] <TB1> INFO: Expecting 41600 events.
[10:02:08.324] <TB1> INFO: 41600 events read in total (2466ms).
[10:02:08.325] <TB1> INFO: Test took 3328ms.
[10:02:08.770] <TB1> INFO: Expecting 41600 events.
[10:02:11.921] <TB1> INFO: 41600 events read in total (2560ms).
[10:02:11.922] <TB1> INFO: Test took 3384ms.
[10:02:12.136] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:12.225] <TB1> INFO: Expecting 2560 events.
[10:02:13.108] <TB1> INFO: 2560 events read in total (292ms).
[10:02:13.109] <TB1> INFO: Test took 973ms.
[10:02:13.111] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:13.417] <TB1> INFO: Expecting 2560 events.
[10:02:14.304] <TB1> INFO: 2560 events read in total (296ms).
[10:02:14.304] <TB1> INFO: Test took 1193ms.
[10:02:14.306] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:14.613] <TB1> INFO: Expecting 2560 events.
[10:02:15.496] <TB1> INFO: 2560 events read in total (292ms).
[10:02:15.497] <TB1> INFO: Test took 1191ms.
[10:02:15.499] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:15.805] <TB1> INFO: Expecting 2560 events.
[10:02:16.688] <TB1> INFO: 2560 events read in total (292ms).
[10:02:16.688] <TB1> INFO: Test took 1189ms.
[10:02:16.690] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:16.996] <TB1> INFO: Expecting 2560 events.
[10:02:17.880] <TB1> INFO: 2560 events read in total (292ms).
[10:02:17.880] <TB1> INFO: Test took 1190ms.
[10:02:17.882] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:18.189] <TB1> INFO: Expecting 2560 events.
[10:02:19.071] <TB1> INFO: 2560 events read in total (291ms).
[10:02:19.071] <TB1> INFO: Test took 1189ms.
[10:02:19.073] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:19.379] <TB1> INFO: Expecting 2560 events.
[10:02:20.263] <TB1> INFO: 2560 events read in total (292ms).
[10:02:20.264] <TB1> INFO: Test took 1191ms.
[10:02:20.266] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:20.572] <TB1> INFO: Expecting 2560 events.
[10:02:21.454] <TB1> INFO: 2560 events read in total (291ms).
[10:02:21.454] <TB1> INFO: Test took 1188ms.
[10:02:21.456] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:21.763] <TB1> INFO: Expecting 2560 events.
[10:02:22.643] <TB1> INFO: 2560 events read in total (289ms).
[10:02:22.644] <TB1> INFO: Test took 1188ms.
[10:02:22.645] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:22.952] <TB1> INFO: Expecting 2560 events.
[10:02:23.833] <TB1> INFO: 2560 events read in total (290ms).
[10:02:23.833] <TB1> INFO: Test took 1188ms.
[10:02:23.835] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:24.141] <TB1> INFO: Expecting 2560 events.
[10:02:25.025] <TB1> INFO: 2560 events read in total (292ms).
[10:02:25.025] <TB1> INFO: Test took 1190ms.
[10:02:25.027] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:25.334] <TB1> INFO: Expecting 2560 events.
[10:02:26.213] <TB1> INFO: 2560 events read in total (288ms).
[10:02:26.213] <TB1> INFO: Test took 1186ms.
[10:02:26.215] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:26.521] <TB1> INFO: Expecting 2560 events.
[10:02:27.401] <TB1> INFO: 2560 events read in total (288ms).
[10:02:27.401] <TB1> INFO: Test took 1186ms.
[10:02:27.403] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:27.709] <TB1> INFO: Expecting 2560 events.
[10:02:28.588] <TB1> INFO: 2560 events read in total (287ms).
[10:02:28.589] <TB1> INFO: Test took 1186ms.
[10:02:28.591] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:28.897] <TB1> INFO: Expecting 2560 events.
[10:02:29.777] <TB1> INFO: 2560 events read in total (289ms).
[10:02:29.778] <TB1> INFO: Test took 1187ms.
[10:02:29.780] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:30.086] <TB1> INFO: Expecting 2560 events.
[10:02:30.964] <TB1> INFO: 2560 events read in total (287ms).
[10:02:30.965] <TB1> INFO: Test took 1185ms.
[10:02:30.968] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:31.273] <TB1> INFO: Expecting 2560 events.
[10:02:32.152] <TB1> INFO: 2560 events read in total (287ms).
[10:02:32.152] <TB1> INFO: Test took 1184ms.
[10:02:32.154] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:32.461] <TB1> INFO: Expecting 2560 events.
[10:02:33.339] <TB1> INFO: 2560 events read in total (287ms).
[10:02:33.339] <TB1> INFO: Test took 1185ms.
[10:02:33.341] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:33.648] <TB1> INFO: Expecting 2560 events.
[10:02:34.527] <TB1> INFO: 2560 events read in total (287ms).
[10:02:34.527] <TB1> INFO: Test took 1186ms.
[10:02:34.529] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:34.836] <TB1> INFO: Expecting 2560 events.
[10:02:35.719] <TB1> INFO: 2560 events read in total (292ms).
[10:02:35.719] <TB1> INFO: Test took 1190ms.
[10:02:35.721] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:36.028] <TB1> INFO: Expecting 2560 events.
[10:02:36.911] <TB1> INFO: 2560 events read in total (292ms).
[10:02:36.912] <TB1> INFO: Test took 1191ms.
[10:02:36.914] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:37.220] <TB1> INFO: Expecting 2560 events.
[10:02:38.100] <TB1> INFO: 2560 events read in total (289ms).
[10:02:38.100] <TB1> INFO: Test took 1186ms.
[10:02:38.102] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:38.408] <TB1> INFO: Expecting 2560 events.
[10:02:39.287] <TB1> INFO: 2560 events read in total (287ms).
[10:02:39.287] <TB1> INFO: Test took 1185ms.
[10:02:39.289] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:39.596] <TB1> INFO: Expecting 2560 events.
[10:02:40.479] <TB1> INFO: 2560 events read in total (292ms).
[10:02:40.479] <TB1> INFO: Test took 1190ms.
[10:02:40.481] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:40.787] <TB1> INFO: Expecting 2560 events.
[10:02:41.673] <TB1> INFO: 2560 events read in total (294ms).
[10:02:41.673] <TB1> INFO: Test took 1193ms.
[10:02:41.675] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:41.982] <TB1> INFO: Expecting 2560 events.
[10:02:42.866] <TB1> INFO: 2560 events read in total (292ms).
[10:02:42.866] <TB1> INFO: Test took 1191ms.
[10:02:42.868] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:43.175] <TB1> INFO: Expecting 2560 events.
[10:02:44.059] <TB1> INFO: 2560 events read in total (293ms).
[10:02:44.059] <TB1> INFO: Test took 1191ms.
[10:02:44.061] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:44.367] <TB1> INFO: Expecting 2560 events.
[10:02:45.254] <TB1> INFO: 2560 events read in total (295ms).
[10:02:45.254] <TB1> INFO: Test took 1193ms.
[10:02:45.256] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:45.562] <TB1> INFO: Expecting 2560 events.
[10:02:46.445] <TB1> INFO: 2560 events read in total (291ms).
[10:02:46.445] <TB1> INFO: Test took 1189ms.
[10:02:46.447] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:46.753] <TB1> INFO: Expecting 2560 events.
[10:02:47.637] <TB1> INFO: 2560 events read in total (292ms).
[10:02:47.637] <TB1> INFO: Test took 1190ms.
[10:02:47.639] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:47.945] <TB1> INFO: Expecting 2560 events.
[10:02:48.832] <TB1> INFO: 2560 events read in total (295ms).
[10:02:48.832] <TB1> INFO: Test took 1193ms.
[10:02:48.835] <TB1> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[10:02:49.141] <TB1> INFO: Expecting 2560 events.
[10:02:50.026] <TB1> INFO: 2560 events read in total (293ms).
[10:02:50.026] <TB1> INFO: Test took 1192ms.
[10:02:50.487] <TB1> INFO: PixTestPhOptimization::doTest() done, duration: 641 seconds
[10:02:50.487] <TB1> INFO: PH scale (per ROC): 46 37 34 36 35 40 47 51 46 42 56 30 43 41 47 40
[10:02:50.487] <TB1> INFO: PH offset (per ROC): 126 118 103 116 109 94 108 110 98 95 121 99 95 92 106 114
[10:02:50.492] <TB1> INFO: Decoding statistics:
[10:02:50.492] <TB1> INFO: General information:
[10:02:50.492] <TB1> INFO: 16bit words read: 127888
[10:02:50.492] <TB1> INFO: valid events total: 20480
[10:02:50.492] <TB1> INFO: empty events: 17976
[10:02:50.492] <TB1> INFO: valid events with pixels: 2504
[10:02:50.492] <TB1> INFO: valid pixel hits: 2504
[10:02:50.492] <TB1> INFO: Event errors: 0
[10:02:50.492] <TB1> INFO: start marker: 0
[10:02:50.492] <TB1> INFO: stop marker: 0
[10:02:50.492] <TB1> INFO: overflow: 0
[10:02:50.492] <TB1> INFO: invalid 5bit words: 0
[10:02:50.492] <TB1> INFO: invalid XOR eye diagram: 0
[10:02:50.492] <TB1> INFO: frame (failed synchr.): 0
[10:02:50.492] <TB1> INFO: idle data (no TBM trl): 0
[10:02:50.492] <TB1> INFO: no data (only TBM hdr): 0
[10:02:50.492] <TB1> INFO: TBM errors: 0
[10:02:50.492] <TB1> INFO: flawed TBM headers: 0
[10:02:50.492] <TB1> INFO: flawed TBM trailers: 0
[10:02:50.492] <TB1> INFO: event ID mismatches: 0
[10:02:50.492] <TB1> INFO: ROC errors: 0
[10:02:50.492] <TB1> INFO: missing ROC header(s): 0
[10:02:50.492] <TB1> INFO: misplaced readback start: 0
[10:02:50.492] <TB1> INFO: Pixel decoding errors: 0
[10:02:50.492] <TB1> INFO: pixel data incomplete: 0
[10:02:50.492] <TB1> INFO: pixel address: 0
[10:02:50.492] <TB1> INFO: pulse height fill bit: 0
[10:02:50.492] <TB1> INFO: buffer corruption: 0
[10:02:50.761] <TB1> INFO: ######################################################################
[10:02:50.761] <TB1> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[10:02:50.761] <TB1> INFO: ######################################################################
[10:02:50.774] <TB1> INFO: scanning low vcal = 10
[10:02:51.009] <TB1> INFO: Expecting 41600 events.
[10:02:54.604] <TB1> INFO: 41600 events read in total (3003ms).
[10:02:54.604] <TB1> INFO: Test took 3829ms.
[10:02:54.605] <TB1> INFO: scanning low vcal = 20
[10:02:54.905] <TB1> INFO: Expecting 41600 events.
[10:02:58.478] <TB1> INFO: 41600 events read in total (2982ms).
[10:02:58.478] <TB1> INFO: Test took 3872ms.
[10:02:58.480] <TB1> INFO: scanning low vcal = 30
[10:02:58.774] <TB1> INFO: Expecting 41600 events.
[10:03:02.406] <TB1> INFO: 41600 events read in total (3040ms).
[10:03:02.407] <TB1> INFO: Test took 3927ms.
[10:03:02.410] <TB1> INFO: scanning low vcal = 40
[10:03:02.688] <TB1> INFO: Expecting 41600 events.
[10:03:06.699] <TB1> INFO: 41600 events read in total (3420ms).
[10:03:06.700] <TB1> INFO: Test took 4290ms.
[10:03:06.703] <TB1> INFO: scanning low vcal = 50
[10:03:06.980] <TB1> INFO: Expecting 41600 events.
[10:03:10.949] <TB1> INFO: 41600 events read in total (3378ms).
[10:03:10.950] <TB1> INFO: Test took 4247ms.
[10:03:10.953] <TB1> INFO: scanning low vcal = 60
[10:03:11.229] <TB1> INFO: Expecting 41600 events.
[10:03:15.225] <TB1> INFO: 41600 events read in total (3404ms).
[10:03:15.226] <TB1> INFO: Test took 4273ms.
[10:03:15.229] <TB1> INFO: scanning low vcal = 70
[10:03:15.505] <TB1> INFO: Expecting 41600 events.
[10:03:19.494] <TB1> INFO: 41600 events read in total (3397ms).
[10:03:19.495] <TB1> INFO: Test took 4266ms.
[10:03:19.497] <TB1> INFO: scanning low vcal = 80
[10:03:19.774] <TB1> INFO: Expecting 41600 events.
[10:03:23.800] <TB1> INFO: 41600 events read in total (3434ms).
[10:03:23.801] <TB1> INFO: Test took 4303ms.
[10:03:23.803] <TB1> INFO: scanning low vcal = 90
[10:03:24.098] <TB1> INFO: Expecting 41600 events.
[10:03:28.073] <TB1> INFO: 41600 events read in total (3384ms).
[10:03:28.073] <TB1> INFO: Test took 4271ms.
[10:03:28.076] <TB1> INFO: scanning low vcal = 100
[10:03:28.369] <TB1> INFO: Expecting 41600 events.
[10:03:32.369] <TB1> INFO: 41600 events read in total (3408ms).
[10:03:32.370] <TB1> INFO: Test took 4294ms.
[10:03:32.372] <TB1> INFO: scanning low vcal = 110
[10:03:32.665] <TB1> INFO: Expecting 41600 events.
[10:03:36.710] <TB1> INFO: 41600 events read in total (3453ms).
[10:03:36.711] <TB1> INFO: Test took 4339ms.
[10:03:36.714] <TB1> INFO: scanning low vcal = 120
[10:03:36.990] <TB1> INFO: Expecting 41600 events.
[10:03:40.998] <TB1> INFO: 41600 events read in total (3416ms).
[10:03:40.999] <TB1> INFO: Test took 4285ms.
[10:03:40.001] <TB1> INFO: scanning low vcal = 130
[10:03:41.278] <TB1> INFO: Expecting 41600 events.
[10:03:45.251] <TB1> INFO: 41600 events read in total (3381ms).
[10:03:45.251] <TB1> INFO: Test took 4250ms.
[10:03:45.254] <TB1> INFO: scanning low vcal = 140
[10:03:45.530] <TB1> INFO: Expecting 41600 events.
[10:03:49.549] <TB1> INFO: 41600 events read in total (3427ms).
[10:03:49.549] <TB1> INFO: Test took 4295ms.
[10:03:49.552] <TB1> INFO: scanning low vcal = 150
[10:03:49.845] <TB1> INFO: Expecting 41600 events.
[10:03:53.801] <TB1> INFO: 41600 events read in total (3364ms).
[10:03:53.801] <TB1> INFO: Test took 4250ms.
[10:03:53.804] <TB1> INFO: scanning low vcal = 160
[10:03:54.081] <TB1> INFO: Expecting 41600 events.
[10:03:58.104] <TB1> INFO: 41600 events read in total (3432ms).
[10:03:58.105] <TB1> INFO: Test took 4301ms.
[10:03:58.107] <TB1> INFO: scanning low vcal = 170
[10:03:58.384] <TB1> INFO: Expecting 41600 events.
[10:04:02.417] <TB1> INFO: 41600 events read in total (3441ms).
[10:04:02.418] <TB1> INFO: Test took 4310ms.
[10:04:02.421] <TB1> INFO: scanning low vcal = 180
[10:04:02.697] <TB1> INFO: Expecting 41600 events.
[10:04:06.671] <TB1> INFO: 41600 events read in total (3382ms).
[10:04:06.672] <TB1> INFO: Test took 4251ms.
[10:04:06.674] <TB1> INFO: scanning low vcal = 190
[10:04:06.951] <TB1> INFO: Expecting 41600 events.
[10:04:10.952] <TB1> INFO: 41600 events read in total (3409ms).
[10:04:10.952] <TB1> INFO: Test took 4278ms.
[10:04:10.955] <TB1> INFO: scanning low vcal = 200
[10:04:11.232] <TB1> INFO: Expecting 41600 events.
[10:04:15.175] <TB1> INFO: 41600 events read in total (3352ms).
[10:04:15.176] <TB1> INFO: Test took 4221ms.
[10:04:15.178] <TB1> INFO: scanning low vcal = 210
[10:04:15.455] <TB1> INFO: Expecting 41600 events.
[10:04:19.396] <TB1> INFO: 41600 events read in total (3349ms).
[10:04:19.397] <TB1> INFO: Test took 4219ms.
[10:04:19.400] <TB1> INFO: scanning low vcal = 220
[10:04:19.676] <TB1> INFO: Expecting 41600 events.
[10:04:23.691] <TB1> INFO: 41600 events read in total (3423ms).
[10:04:23.692] <TB1> INFO: Test took 4292ms.
[10:04:23.694] <TB1> INFO: scanning low vcal = 230
[10:04:23.971] <TB1> INFO: Expecting 41600 events.
[10:04:27.979] <TB1> INFO: 41600 events read in total (3416ms).
[10:04:27.980] <TB1> INFO: Test took 4285ms.
[10:04:27.983] <TB1> INFO: scanning low vcal = 240
[10:04:28.260] <TB1> INFO: Expecting 41600 events.
[10:04:32.230] <TB1> INFO: 41600 events read in total (3379ms).
[10:04:32.230] <TB1> INFO: Test took 4247ms.
[10:04:32.233] <TB1> INFO: scanning low vcal = 250
[10:04:32.510] <TB1> INFO: Expecting 41600 events.
[10:04:36.519] <TB1> INFO: 41600 events read in total (3418ms).
[10:04:36.519] <TB1> INFO: Test took 4286ms.
[10:04:36.523] <TB1> INFO: scanning high vcal = 30 (= 210 in low range)
[10:04:36.799] <TB1> INFO: Expecting 41600 events.
[10:04:40.846] <TB1> INFO: 41600 events read in total (3455ms).
[10:04:40.847] <TB1> INFO: Test took 4324ms.
[10:04:40.849] <TB1> INFO: scanning high vcal = 50 (= 350 in low range)
[10:04:41.139] <TB1> INFO: Expecting 41600 events.
[10:04:45.110] <TB1> INFO: 41600 events read in total (3379ms).
[10:04:45.110] <TB1> INFO: Test took 4261ms.
[10:04:45.113] <TB1> INFO: scanning high vcal = 70 (= 490 in low range)
[10:04:45.390] <TB1> INFO: Expecting 41600 events.
[10:04:49.374] <TB1> INFO: 41600 events read in total (3393ms).
[10:04:49.375] <TB1> INFO: Test took 4262ms.
[10:04:49.378] <TB1> INFO: scanning high vcal = 90 (= 630 in low range)
[10:04:49.675] <TB1> INFO: Expecting 41600 events.
[10:04:53.692] <TB1> INFO: 41600 events read in total (3425ms).
[10:04:53.693] <TB1> INFO: Test took 4315ms.
[10:04:53.696] <TB1> INFO: scanning high vcal = 200 (= 1400 in low range)
[10:04:53.987] <TB1> INFO: Expecting 41600 events.
[10:04:57.952] <TB1> INFO: 41600 events read in total (3373ms).
[10:04:57.953] <TB1> INFO: Test took 4257ms.
[10:04:58.406] <TB1> INFO: PixTestGainPedestal::measure() done
[10:05:33.897] <TB1> INFO: PixTestGainPedestal::fit() done
[10:05:33.897] <TB1> INFO: non-linearity mean: 0.973 0.940 0.945 0.951 0.938 0.953 0.971 0.961 0.947 0.950 0.981 1.032 0.942 0.956 0.943 0.954
[10:05:33.897] <TB1> INFO: non-linearity RMS: 0.005 0.074 0.154 0.045 0.099 0.039 0.016 0.031 0.057 0.045 0.004 0.176 0.071 0.053 0.049 0.051
[10:05:33.897] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C0.dat
[10:05:33.919] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C1.dat
[10:05:33.941] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C2.dat
[10:05:33.963] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C3.dat
[10:05:33.979] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C4.dat
[10:05:33.993] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C5.dat
[10:05:33.007] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C6.dat
[10:05:34.021] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C7.dat
[10:05:34.034] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C8.dat
[10:05:34.048] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C9.dat
[10:05:34.063] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C10.dat
[10:05:34.077] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C11.dat
[10:05:34.091] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C12.dat
[10:05:34.105] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C13.dat
[10:05:34.125] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C14.dat
[10:05:34.147] <TB1> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1057_FullQualification_2016-10-25_08h37m_1477377432//000_Fulltest_p17//phCalibrationFitErr35_C15.dat
[10:05:34.168] <TB1> INFO: PixTestGainPedestal::fullTest() done, duration: 163 seconds
[10:05:34.168] <TB1> INFO: Decoding statistics:
[10:05:34.168] <TB1> INFO: General information:
[10:05:34.168] <TB1> INFO: 16bit words read: 3311100
[10:05:34.168] <TB1> INFO: valid events total: 332800
[10:05:34.168] <TB1> INFO: empty events: 708
[10:05:34.168] <TB1> INFO: valid events with pixels: 332092
[10:05:34.169] <TB1> INFO: valid pixel hits: 657150
[10:05:34.169] <TB1> INFO: Event errors: 0
[10:05:34.169] <TB1> INFO: start marker: 0
[10:05:34.169] <TB1> INFO: stop marker: 0
[10:05:34.169] <TB1> INFO: overflow: 0
[10:05:34.169] <TB1> INFO: invalid 5bit words: 0
[10:05:34.169] <TB1> INFO: invalid XOR eye diagram: 0
[10:05:34.169] <TB1> INFO: frame (failed synchr.): 0
[10:05:34.169] <TB1> INFO: idle data (no TBM trl): 0
[10:05:34.169] <TB1> INFO: no data (only TBM hdr): 0
[10:05:34.169] <TB1> INFO: TBM errors: 0
[10:05:34.169] <TB1> INFO: flawed TBM headers: 0
[10:05:34.169] <TB1> INFO: flawed TBM trailers: 0
[10:05:34.169] <TB1> INFO: event ID mismatches: 0
[10:05:34.169] <TB1> INFO: ROC errors: 0
[10:05:34.169] <TB1> INFO: missing ROC header(s): 0
[10:05:34.169] <TB1> INFO: misplaced readback start: 0
[10:05:34.169] <TB1> INFO: Pixel decoding errors: 0
[10:05:34.169] <TB1> INFO: pixel data incomplete: 0
[10:05:34.169] <TB1> INFO: pixel address: 0
[10:05:34.169] <TB1> INFO: pulse height fill bit: 0
[10:05:34.169] <TB1> INFO: buffer corruption: 0
[10:05:34.191] <TB1> INFO: Decoding statistics:
[10:05:34.191] <TB1> INFO: General information:
[10:05:34.191] <TB1> INFO: 16bit words read: 3440524
[10:05:34.191] <TB1> INFO: valid events total: 353536
[10:05:34.191] <TB1> INFO: empty events: 18940
[10:05:34.191] <TB1> INFO: valid events with pixels: 334596
[10:05:34.191] <TB1> INFO: valid pixel hits: 659654
[10:05:34.191] <TB1> INFO: Event errors: 0
[10:05:34.191] <TB1> INFO: start marker: 0
[10:05:34.191] <TB1> INFO: stop marker: 0
[10:05:34.191] <TB1> INFO: overflow: 0
[10:05:34.191] <TB1> INFO: invalid 5bit words: 0
[10:05:34.191] <TB1> INFO: invalid XOR eye diagram: 0
[10:05:34.191] <TB1> INFO: frame (failed synchr.): 0
[10:05:34.191] <TB1> INFO: idle data (no TBM trl): 0
[10:05:34.191] <TB1> INFO: no data (only TBM hdr): 0
[10:05:34.191] <TB1> INFO: TBM errors: 0
[10:05:34.191] <TB1> INFO: flawed TBM headers: 0
[10:05:34.191] <TB1> INFO: flawed TBM trailers: 0
[10:05:34.191] <TB1> INFO: event ID mismatches: 0
[10:05:34.191] <TB1> INFO: ROC errors: 0
[10:05:34.191] <TB1> INFO: missing ROC header(s): 0
[10:05:34.191] <TB1> INFO: misplaced readback start: 0
[10:05:34.191] <TB1> INFO: Pixel decoding errors: 0
[10:05:34.191] <TB1> INFO: pixel data incomplete: 0
[10:05:34.191] <TB1> INFO: pixel address: 0
[10:05:34.191] <TB1> INFO: pulse height fill bit: 0
[10:05:34.191] <TB1> INFO: buffer corruption: 0
[10:05:34.191] <TB1> INFO: enter test to run
[10:05:34.191] <TB1> INFO: test: exit no parameter change
[10:05:34.247] <TB1> QUIET: Connection to board 153 closed.
[10:05:34.248] <TB1> INFO: pXar: this is the end, my friend