[12:50:31.196] <TB0> INFO: *** Welcome to pxar ***
[12:50:31.196] <TB0> INFO: *** Today: 2016/10/31
[12:50:31.204] <TB0> INFO: *** Version: c8ba-dirty
[12:50:31.204] <TB0> INFO: readRocDacs: /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:50:31.205] <TB0> INFO: readTbmDacs: /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C0a.dat .. /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:50:31.205] <TB0> INFO: readMaskFile: /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//defaultMaskFile.dat
[12:50:31.205] <TB0> INFO: readTrimFile: /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters_C0.dat .. /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters_C15.dat
[12:50:31.264] <TB0> INFO: clk: 4
[12:50:31.265] <TB0> INFO: ctr: 4
[12:50:31.265] <TB0> INFO: sda: 19
[12:50:31.265] <TB0> INFO: tin: 9
[12:50:31.265] <TB0> INFO: level: 15
[12:50:31.265] <TB0> INFO: triggerdelay: 0
[12:50:31.265] <TB0> QUIET: Instanciating API for pxar v2.7.6+61~g7f4a123
[12:50:31.265] <TB0> INFO: Log level: INFO
[12:50:31.273] <TB0> INFO: Found DTB DTB_WRQ4OZ
[12:50:31.283] <TB0> QUIET: Connection to board DTB_WRQ4OZ opened.
[12:50:31.285] <TB0> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 71
HW version: DTB1.2
FW version: 4.6
SW version: 4.7
Options:
USB id: DTB_WRQ4OZ
MAC address: 40D855118047
Hostname: pixelDTB071
Comment:
------------------------------------------------------
[12:50:31.287] <TB0> INFO: RPC call hashes of host and DTB match: 486171790
[12:50:32.773] <TB0> INFO: DUT info:
[12:50:32.773] <TB0> INFO: The DUT currently contains the following objects:
[12:50:32.773] <TB0> INFO: 4 TBM Cores tbm10c (4 ON)
[12:50:32.773] <TB0> INFO: TBM Core alpha (0): 7 registers set
[12:50:32.773] <TB0> INFO: TBM Core beta (1): 7 registers set
[12:50:32.773] <TB0> INFO: TBM Core alpha (2): 7 registers set
[12:50:32.773] <TB0> INFO: TBM Core beta (3): 7 registers set
[12:50:32.773] <TB0> INFO: 16 ROCs proc600 (16 ON) with 4160 pixelConfigs
[12:50:32.773] <TB0> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:32.773] <TB0> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[12:50:33.175] <TB0> INFO: enter 'restricted' command line mode
[12:50:33.175] <TB0> INFO: enter test to run
[12:50:33.176] <TB0> INFO: test: pretest no parameter change
[12:50:33.176] <TB0> INFO: running: pretest
[12:50:33.181] <TB0> INFO: ######################################################################
[12:50:33.181] <TB0> INFO: PixTestPretest::doTest()
[12:50:33.181] <TB0> INFO: ######################################################################
[12:50:33.182] <TB0> INFO: ----------------------------------------------------------------------
[12:50:33.182] <TB0> INFO: PixTestPretest::programROC()
[12:50:33.182] <TB0> INFO: ----------------------------------------------------------------------
[12:50:51.196] <TB0> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[12:50:51.196] <TB0> INFO: IA differences per ROC: 15.3 19.3 18.5 18.5 19.3 16.9 20.9 19.3 19.3 20.1 18.5 18.5 19.3 20.1 18.5 20.1
[12:50:51.263] <TB0> INFO: ----------------------------------------------------------------------
[12:50:51.263] <TB0> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[12:50:51.263] <TB0> INFO: ----------------------------------------------------------------------
[12:51:00.055] <TB0> INFO: PixTestPretest::setVana() done, Module Ia 383.5 mA = 23.9688 mA/ROC
[12:51:00.055] <TB0> INFO: i(loss) [mA/ROC]: 20.1 19.3 20.1 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3 19.3
[12:51:00.086] <TB0> INFO: ----------------------------------------------------------------------
[12:51:00.086] <TB0> INFO: PixTestPretest::findTiming()
[12:51:00.086] <TB0> INFO: ----------------------------------------------------------------------
[12:51:00.086] <TB0> INFO: PixTestCmd::init()

[12:51:32.620] <TB0> INFO: TBM phases: 160MHz: 0, 400MHz: 2, TBM delays: ROC(0/1):5, header/trailer: 1, token: 1
[12:51:32.620] <TB0> INFO: (success/tries = 100/100), width = 4
[12:51:34.121] <TB0> INFO: ----------------------------------------------------------------------
[12:51:34.121] <TB0> INFO: PixTestPretest::findWorkingPixel()
[12:51:34.121] <TB0> INFO: ----------------------------------------------------------------------
[12:51:34.216] <TB0> INFO: Expecting 231680 events.
[12:51:44.340] <TB0> INFO: 231680 events read in total (9533ms).
[12:51:44.352] <TB0> INFO: Test took 10227ms.
[12:51:44.603] <TB0> INFO: Found working pixel in all ROCs: col/row = 12/22
[12:51:44.638] <TB0> INFO: ----------------------------------------------------------------------
[12:51:44.638] <TB0> INFO: PixTestPretest::setVthrCompCalDel()
[12:51:44.638] <TB0> INFO: ----------------------------------------------------------------------
[12:51:44.736] <TB0> INFO: Expecting 231680 events.
[12:51:54.918] <TB0> INFO: 231680 events read in total (9591ms).
[12:51:54.931] <TB0> INFO: Test took 10286ms.
[12:51:55.184] <TB0> INFO: PixTestPretest::setVthrCompCalDel() done
[12:51:55.184] <TB0> INFO: CalDel: 96 80 84 100 92 78 82 107 88 78 87 91 93 123 81 84
[12:51:55.184] <TB0> INFO: VthrComp: 51 51 51 51 51 51 51 51 54 53 54 52 51 51 52 51
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C0.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C1.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C2.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C3.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C4.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C5.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C6.dat
[12:51:55.187] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C7.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C8.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C9.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C10.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C11.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C12.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C13.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C14.dat
[12:51:55.188] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters_C15.dat
[12:51:55.188] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C0a.dat
[12:51:55.188] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C0b.dat
[12:51:55.188] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C1a.dat
[12:51:55.189] <TB0> INFO: write tbm parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//tbmParameters_C1b.dat
[12:51:55.189] <TB0> INFO: PixTestPretest::doTest() done, duration: 82 seconds
[12:51:55.242] <TB0> INFO: enter test to run
[12:51:55.242] <TB0> INFO: test: fulltest no parameter change
[12:51:55.242] <TB0> INFO: running: fulltest
[12:51:55.242] <TB0> INFO: ######################################################################
[12:51:55.242] <TB0> INFO: PixTestFullTest::doTest()
[12:51:55.242] <TB0> INFO: ######################################################################
[12:51:55.243] <TB0> INFO: ######################################################################
[12:51:55.243] <TB0> INFO: PixTestAlive::doTest()
[12:51:55.243] <TB0> INFO: ######################################################################
[12:51:55.245] <TB0> INFO: ----------------------------------------------------------------------
[12:51:55.245] <TB0> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:51:55.245] <TB0> INFO: ----------------------------------------------------------------------
[12:51:55.483] <TB0> INFO: Expecting 41600 events.
[12:51:59.065] <TB0> INFO: 41600 events read in total (2991ms).
[12:51:59.066] <TB0> INFO: Test took 3819ms.
[12:51:59.298] <TB0> INFO: PixTestAlive::aliveTest() done
[12:51:59.298] <TB0> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:51:59.299] <TB0> INFO: ----------------------------------------------------------------------
[12:51:59.299] <TB0> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:51:59.299] <TB0> INFO: ----------------------------------------------------------------------
[12:51:59.542] <TB0> INFO: Expecting 41600 events.
[12:52:02.567] <TB0> INFO: 41600 events read in total (2433ms).
[12:52:02.567] <TB0> INFO: Test took 3265ms.
[12:52:02.567] <TB0> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[12:52:02.805] <TB0> INFO: PixTestAlive::maskTest() done
[12:52:02.805] <TB0> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:52:02.807] <TB0> INFO: ----------------------------------------------------------------------
[12:52:02.807] <TB0> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[12:52:02.807] <TB0> INFO: ----------------------------------------------------------------------
[12:52:03.061] <TB0> INFO: Expecting 41600 events.
[12:52:06.552] <TB0> INFO: 41600 events read in total (2899ms).
[12:52:06.553] <TB0> INFO: Test took 3743ms.
[12:52:06.789] <TB0> INFO: PixTestAlive::addressDecodingTest() done
[12:52:06.789] <TB0> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[12:52:06.790] <TB0> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[12:52:06.790] <TB0> INFO: Decoding statistics:
[12:52:06.790] <TB0> INFO: General information:
[12:52:06.790] <TB0> INFO: 16bit words read: 0
[12:52:06.790] <TB0> INFO: valid events total: 0
[12:52:06.790] <TB0> INFO: empty events: 0
[12:52:06.790] <TB0> INFO: valid events with pixels: 0
[12:52:06.790] <TB0> INFO: valid pixel hits: 0
[12:52:06.790] <TB0> INFO: Event errors: 0
[12:52:06.790] <TB0> INFO: start marker: 0
[12:52:06.790] <TB0> INFO: stop marker: 0
[12:52:06.790] <TB0> INFO: overflow: 0
[12:52:06.790] <TB0> INFO: invalid 5bit words: 0
[12:52:06.790] <TB0> INFO: invalid XOR eye diagram: 0
[12:52:06.790] <TB0> INFO: frame (failed synchr.): 0
[12:52:06.790] <TB0> INFO: idle data (no TBM trl): 0
[12:52:06.790] <TB0> INFO: no data (only TBM hdr): 0
[12:52:06.790] <TB0> INFO: TBM errors: 0
[12:52:06.790] <TB0> INFO: flawed TBM headers: 0
[12:52:06.790] <TB0> INFO: flawed TBM trailers: 0
[12:52:06.790] <TB0> INFO: event ID mismatches: 0
[12:52:06.790] <TB0> INFO: ROC errors: 0
[12:52:06.790] <TB0> INFO: missing ROC header(s): 0
[12:52:06.790] <TB0> INFO: misplaced readback start: 0
[12:52:06.790] <TB0> INFO: Pixel decoding errors: 0
[12:52:06.790] <TB0> INFO: pixel data incomplete: 0
[12:52:06.790] <TB0> INFO: pixel address: 0
[12:52:06.790] <TB0> INFO: pulse height fill bit: 0
[12:52:06.790] <TB0> INFO: buffer corruption: 0
[12:52:06.798] <TB0> INFO: readReadbackCal: /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat .. /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:52:06.798] <TB0> INFO: readGainPedestalParameters /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr_C0.dat .. /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr_C15.dat

[12:52:06.799] <TB0> INFO: ######################################################################
[12:52:06.799] <TB0> INFO: PixTestReadback::doTest()
[12:52:06.799] <TB0> INFO: ######################################################################
[12:52:06.799] <TB0> INFO: ----------------------------------------------------------------------
[12:52:06.799] <TB0> INFO: PixTestReadback::CalibrateVd()
[12:52:06.799] <TB0> INFO: ----------------------------------------------------------------------
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:52:16.768] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:52:16.769] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:52:16.770] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:52:16.800] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:52:16.801] <TB0> INFO: ----------------------------------------------------------------------
[12:52:16.801] <TB0> INFO: PixTestReadback::CalibrateVa()
[12:52:16.801] <TB0> INFO: ----------------------------------------------------------------------
[12:52:26.716] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:52:26.716] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:52:26.717] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:52:26.746] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:52:26.746] <TB0> INFO: ----------------------------------------------------------------------
[12:52:26.746] <TB0> INFO: PixTestReadback::readbackVbg()
[12:52:26.746] <TB0> INFO: ----------------------------------------------------------------------
[12:52:34.405] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:52:34.405] <TB0> INFO: ----------------------------------------------------------------------
[12:52:34.405] <TB0> INFO: PixTestReadback::getCalibratedVbg()
[12:52:34.405] <TB0> INFO: ----------------------------------------------------------------------
[12:52:34.405] <TB0> INFO: Vbg will be calibrated using Vd calibration
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 153.6calibrated Vbg = 1.18717 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 156.1calibrated Vbg = 1.19063 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 154.3calibrated Vbg = 1.18708 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 144calibrated Vbg = 1.17233 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 162.2calibrated Vbg = 1.18276 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 147.1calibrated Vbg = 1.18355 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 156.6calibrated Vbg = 1.18998 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 153.9calibrated Vbg = 1.18711 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 158calibrated Vbg = 1.17962 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 156.5calibrated Vbg = 1.17748 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 152.6calibrated Vbg = 1.17437 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 153calibrated Vbg = 1.17553 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 154.4calibrated Vbg = 1.17544 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 151.5calibrated Vbg = 1.18501 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 157calibrated Vbg = 1.185 :::*/*/*/*/
[12:52:34.405] <TB0> INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 155.1calibrated Vbg = 1.18697 :::*/*/*/*/
[12:52:34.409] <TB0> INFO: ----------------------------------------------------------------------
[12:52:34.409] <TB0> INFO: PixTestReadback::CalibrateIa()
[12:52:34.409] <TB0> INFO: ----------------------------------------------------------------------
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C0.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C1.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C2.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C3.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C4.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C5.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C6.dat
[12:55:15.236] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C7.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C8.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C9.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C10.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C11.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C12.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C13.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C14.dat
[12:55:15.237] <TB0> INFO: write readback calibration parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//readbackCal_C15.dat
[12:55:15.267] <TB0> INFO: PixTestPattern:: pg_setup set to default.
[12:55:15.269] <TB0> INFO: PixTestReadback::doTest() done
[12:55:15.269] <TB0> INFO: Decoding statistics:
[12:55:15.269] <TB0> INFO: General information:
[12:55:15.269] <TB0> INFO: 16bit words read: 1536
[12:55:15.269] <TB0> INFO: valid events total: 256
[12:55:15.269] <TB0> INFO: empty events: 256
[12:55:15.269] <TB0> INFO: valid events with pixels: 0
[12:55:15.269] <TB0> INFO: valid pixel hits: 0
[12:55:15.269] <TB0> INFO: Event errors: 0
[12:55:15.270] <TB0> INFO: start marker: 0
[12:55:15.270] <TB0> INFO: stop marker: 0
[12:55:15.270] <TB0> INFO: overflow: 0
[12:55:15.270] <TB0> INFO: invalid 5bit words: 0
[12:55:15.270] <TB0> INFO: invalid XOR eye diagram: 0
[12:55:15.270] <TB0> INFO: frame (failed synchr.): 0
[12:55:15.270] <TB0> INFO: idle data (no TBM trl): 0
[12:55:15.270] <TB0> INFO: no data (only TBM hdr): 0
[12:55:15.270] <TB0> INFO: TBM errors: 0
[12:55:15.270] <TB0> INFO: flawed TBM headers: 0
[12:55:15.270] <TB0> INFO: flawed TBM trailers: 0
[12:55:15.270] <TB0> INFO: event ID mismatches: 0
[12:55:15.270] <TB0> INFO: ROC errors: 0
[12:55:15.270] <TB0> INFO: missing ROC header(s): 0
[12:55:15.270] <TB0> INFO: misplaced readback start: 0
[12:55:15.270] <TB0> INFO: Pixel decoding errors: 0
[12:55:15.270] <TB0> INFO: pixel data incomplete: 0
[12:55:15.270] <TB0> INFO: pixel address: 0
[12:55:15.270] <TB0> INFO: pulse height fill bit: 0
[12:55:15.270] <TB0> INFO: buffer corruption: 0
[12:55:15.324] <TB0> INFO: ######################################################################
[12:55:15.324] <TB0> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[12:55:15.324] <TB0> INFO: ######################################################################
[12:55:15.328] <TB0> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (-1/-1) hits flags = 514 (plus default)
[12:55:15.439] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[12:55:15.439] <TB0> INFO: run 1 of 1
[12:55:15.677] <TB0> INFO: Expecting 3120000 events.
[12:55:48.339] <TB0> INFO: 675465 events read in total (32070ms).











[12:56:19.294] <TB0> INFO: 1345980 events read in total (63025ms).




















[12:56:49.833] <TB0> INFO: 2015060 events read in total (93564ms).
[12:57:20.494] <TB0> INFO: 2682755 events read in total (124225ms).











[12:57:40.615] <TB0> INFO: 3120000 events read in total (144346ms).
[12:57:40.697] <TB0> INFO: Test took 145259ms.
[12:58:02.767] <TB0> INFO: PixTestBBMap::doTest() done with 3 decoding errors: , duration: 167 seconds
[12:58:02.767] <TB0> INFO: number of dead bumps (per ROC): 0 0 0 0 0 0 1 2 0 0 0 1 0 1 0 0
[12:58:02.767] <TB0> INFO: separation cut (per ROC): 103 105 103 101 106 101 124 116 121 122 121 118 102 111 122 114
[12:58:02.767] <TB0> INFO: Decoding statistics:
[12:58:02.767] <TB0> INFO: General information:
[12:58:02.767] <TB0> INFO: 16bit words read: 0
[12:58:02.767] <TB0> INFO: valid events total: 0
[12:58:02.767] <TB0> INFO: empty events: 0
[12:58:02.767] <TB0> INFO: valid events with pixels: 0
[12:58:02.767] <TB0> INFO: valid pixel hits: 0
[12:58:02.767] <TB0> INFO: Event errors: 0
[12:58:02.767] <TB0> INFO: start marker: 0
[12:58:02.767] <TB0> INFO: stop marker: 0
[12:58:02.767] <TB0> INFO: overflow: 0
[12:58:02.767] <TB0> INFO: invalid 5bit words: 0
[12:58:02.767] <TB0> INFO: invalid XOR eye diagram: 0
[12:58:02.767] <TB0> INFO: frame (failed synchr.): 0
[12:58:02.767] <TB0> INFO: idle data (no TBM trl): 0
[12:58:02.767] <TB0> INFO: no data (only TBM hdr): 0
[12:58:02.767] <TB0> INFO: TBM errors: 0
[12:58:02.767] <TB0> INFO: flawed TBM headers: 0
[12:58:02.767] <TB0> INFO: flawed TBM trailers: 0
[12:58:02.767] <TB0> INFO: event ID mismatches: 0
[12:58:02.767] <TB0> INFO: ROC errors: 0
[12:58:02.767] <TB0> INFO: missing ROC header(s): 0
[12:58:02.767] <TB0> INFO: misplaced readback start: 0
[12:58:02.767] <TB0> INFO: Pixel decoding errors: 0
[12:58:02.767] <TB0> INFO: pixel data incomplete: 0
[12:58:02.767] <TB0> INFO: pixel address: 0
[12:58:02.767] <TB0> INFO: pulse height fill bit: 0
[12:58:02.767] <TB0> INFO: buffer corruption: 0
[12:58:02.817] <TB0> INFO: ######################################################################
[12:58:02.817] <TB0> INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:58:02.817] <TB0> INFO: ######################################################################
[12:58:02.818] <TB0> INFO: ----------------------------------------------------------------------
[12:58:02.818] <TB0> INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[12:58:02.818] <TB0> INFO: ----------------------------------------------------------------------
[12:58:02.818] <TB0> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 25 .. 200 (-1/-1) hits flags = 528 (plus default)
[12:58:02.832] <TB0> INFO: dacScan split into 1 runs with ntrig = 50
[12:58:02.832] <TB0> INFO: run 1 of 1
[12:58:03.157] <TB0> INFO: Expecting 36608000 events.
[12:58:29.155] <TB0> INFO: 698150 events read in total (25406ms).
[12:58:52.379] <TB0> INFO: 1381250 events read in total (48630ms).
[12:59:15.946] <TB0> INFO: 2066650 events read in total (72197ms).
[12:59:39.395] <TB0> INFO: 2749100 events read in total (95646ms).
[13:00:02.877] <TB0> INFO: 3431600 events read in total (119128ms).
[13:00:26.099] <TB0> INFO: 4113500 events read in total (142350ms).
[13:00:49.313] <TB0> INFO: 4795150 events read in total (165564ms).
[13:01:12.537] <TB0> INFO: 5476250 events read in total (188788ms).
[13:01:35.739] <TB0> INFO: 6158100 events read in total (211990ms).
[13:01:59.196] <TB0> INFO: 6836750 events read in total (235447ms).
[13:02:22.381] <TB0> INFO: 7515250 events read in total (258632ms).
[13:02:45.456] <TB0> INFO: 8194700 events read in total (281707ms).
[13:03:08.841] <TB0> INFO: 8875250 events read in total (305092ms).
[13:03:31.000] <TB0> INFO: 9554350 events read in total (328251ms).
[13:03:55.234] <TB0> INFO: 10233450 events read in total (351485ms).
[13:04:18.482] <TB0> INFO: 10912150 events read in total (374733ms).
[13:04:41.432] <TB0> INFO: 11589400 events read in total (397683ms).
[13:05:04.548] <TB0> INFO: 12267000 events read in total (420799ms).
[13:05:27.562] <TB0> INFO: 12944400 events read in total (443813ms).
[13:05:50.910] <TB0> INFO: 13622750 events read in total (467161ms).
[13:06:14.092] <TB0> INFO: 14298350 events read in total (490343ms).
[13:06:37.186] <TB0> INFO: 14973850 events read in total (513437ms).
[13:07:00.382] <TB0> INFO: 15645800 events read in total (536633ms).
[13:07:23.862] <TB0> INFO: 16321850 events read in total (560113ms).
[13:07:47.011] <TB0> INFO: 16994000 events read in total (583262ms).
[13:08:10.313] <TB0> INFO: 17670300 events read in total (606564ms).
[13:08:33.312] <TB0> INFO: 18341600 events read in total (629563ms).
[13:08:56.439] <TB0> INFO: 19017400 events read in total (652690ms).
[13:09:19.576] <TB0> INFO: 19688500 events read in total (675827ms).
[13:09:43.178] <TB0> INFO: 20361150 events read in total (699429ms).
[13:10:06.409] <TB0> INFO: 21030150 events read in total (722660ms).
[13:10:29.881] <TB0> INFO: 21704500 events read in total (746132ms).
[13:10:52.887] <TB0> INFO: 22374850 events read in total (769138ms).
[13:11:16.209] <TB0> INFO: 23046750 events read in total (792460ms).
[13:11:39.234] <TB0> INFO: 23716000 events read in total (815485ms).
[13:12:02.616] <TB0> INFO: 24388450 events read in total (838867ms).
[13:12:26.026] <TB0> INFO: 25059500 events read in total (862277ms).
[13:12:49.441] <TB0> INFO: 25729750 events read in total (885692ms).
[13:13:12.869] <TB0> INFO: 26399300 events read in total (909120ms).
[13:13:36.012] <TB0> INFO: 27067700 events read in total (932263ms).
[13:13:59.330] <TB0> INFO: 27735950 events read in total (955581ms).
[13:14:22.715] <TB0> INFO: 28403800 events read in total (978966ms).
[13:14:45.984] <TB0> INFO: 29071900 events read in total (1002235ms).
[13:15:09.137] <TB0> INFO: 29737150 events read in total (1025388ms).
[13:15:32.496] <TB0> INFO: 30403500 events read in total (1048747ms).
[13:15:55.669] <TB0> INFO: 31068800 events read in total (1071920ms).
[13:16:18.874] <TB0> INFO: 31737500 events read in total (1095125ms).
[13:16:42.005] <TB0> INFO: 32405050 events read in total (1118256ms).
[13:17:05.384] <TB0> INFO: 33073450 events read in total (1141635ms).
[13:17:28.711] <TB0> INFO: 33739900 events read in total (1164962ms).
[13:17:52.110] <TB0> INFO: 34412050 events read in total (1188361ms).
[13:18:15.493] <TB0> INFO: 35079600 events read in total (1211744ms).
[13:18:38.719] <TB0> INFO: 35751650 events read in total (1234970ms).
[13:19:01.937] <TB0> INFO: 36432350 events read in total (1258188ms).
[13:19:08.441] <TB0> INFO: 36608000 events read in total (1264692ms).
[13:19:08.545] <TB0> INFO: Test took 1265712ms.
[13:19:08.996] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:10.466] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:11.929] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:13.940] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:15.524] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:17.275] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:19.196] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:21.208] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:23.268] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:25.440] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:27.626] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:29.843] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:31.834] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:33.666] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:35.728] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:37.551] <TB0> INFO: dumping ASCII scurve output file: SCurveData
[13:19:39.642] <TB0> INFO: PixTestScurves::scurves() done
[13:19:39.642] <TB0> INFO: Vcal mean: 132.24 123.32 125.40 113.33 120.74 114.85 135.08 129.92 127.54 130.49 132.03 137.38 122.57 125.03 129.35 123.94
[13:19:39.642] <TB0> INFO: Vcal RMS: 6.67 5.71 6.32 5.10 6.53 6.09 7.14 6.23 6.24 6.68 7.16 6.72 6.83 6.12 6.40 5.99
[13:19:39.642] <TB0> INFO: PixTestScurves::fullTest() done, duration: 1296 seconds
[13:19:39.642] <TB0> INFO: Decoding statistics:
[13:19:39.642] <TB0> INFO: General information:
[13:19:39.642] <TB0> INFO: 16bit words read: 0
[13:19:39.642] <TB0> INFO: valid events total: 0
[13:19:39.642] <TB0> INFO: empty events: 0
[13:19:39.643] <TB0> INFO: valid events with pixels: 0
[13:19:39.643] <TB0> INFO: valid pixel hits: 0
[13:19:39.643] <TB0> INFO: Event errors: 0
[13:19:39.643] <TB0> INFO: start marker: 0
[13:19:39.643] <TB0> INFO: stop marker: 0
[13:19:39.643] <TB0> INFO: overflow: 0
[13:19:39.643] <TB0> INFO: invalid 5bit words: 0
[13:19:39.643] <TB0> INFO: invalid XOR eye diagram: 0
[13:19:39.643] <TB0> INFO: frame (failed synchr.): 0
[13:19:39.643] <TB0> INFO: idle data (no TBM trl): 0
[13:19:39.643] <TB0> INFO: no data (only TBM hdr): 0
[13:19:39.643] <TB0> INFO: TBM errors: 0
[13:19:39.643] <TB0> INFO: flawed TBM headers: 0
[13:19:39.643] <TB0> INFO: flawed TBM trailers: 0
[13:19:39.643] <TB0> INFO: event ID mismatches: 0
[13:19:39.643] <TB0> INFO: ROC errors: 0
[13:19:39.643] <TB0> INFO: missing ROC header(s): 0
[13:19:39.643] <TB0> INFO: misplaced readback start: 0
[13:19:39.643] <TB0> INFO: Pixel decoding errors: 0
[13:19:39.643] <TB0> INFO: pixel data incomplete: 0
[13:19:39.643] <TB0> INFO: pixel address: 0
[13:19:39.643] <TB0> INFO: pulse height fill bit: 0
[13:19:39.643] <TB0> INFO: buffer corruption: 0
[13:19:39.736] <TB0> INFO: ######################################################################
[13:19:39.736] <TB0> INFO: PixTestTrim::doTest()
[13:19:39.736] <TB0> INFO: ######################################################################
[13:19:39.737] <TB0> INFO: ----------------------------------------------------------------------
[13:19:39.737] <TB0> INFO: PixTestTrim::trimTest() ntrig = 8, vcal = 35
[13:19:39.737] <TB0> INFO: ----------------------------------------------------------------------
[13:19:39.805] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[13:19:39.805] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:19:39.820] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:19:39.820] <TB0> INFO: run 1 of 1
[13:19:40.144] <TB0> INFO: Expecting 5025280 events.
[13:20:12.132] <TB0> INFO: 834400 events read in total (31383ms).
[13:20:42.783] <TB0> INFO: 1665800 events read in total (62035ms).
[13:21:13.455] <TB0> INFO: 2493656 events read in total (92706ms).
[13:21:44.219] <TB0> INFO: 3319336 events read in total (123470ms).
[13:22:14.724] <TB0> INFO: 4141576 events read in total (153976ms).
[13:22:45.402] <TB0> INFO: 4963104 events read in total (184653ms).
[13:22:48.114] <TB0> INFO: 5025280 events read in total (187365ms).
[13:22:48.178] <TB0> INFO: Test took 188358ms.
[13:23:06.703] <TB0> INFO: ROC 0 VthrComp = 127
[13:23:06.703] <TB0> INFO: ROC 1 VthrComp = 126
[13:23:06.703] <TB0> INFO: ROC 2 VthrComp = 122
[13:23:06.703] <TB0> INFO: ROC 3 VthrComp = 113
[13:23:06.703] <TB0> INFO: ROC 4 VthrComp = 119
[13:23:06.704] <TB0> INFO: ROC 5 VthrComp = 111
[13:23:06.704] <TB0> INFO: ROC 6 VthrComp = 130
[13:23:06.704] <TB0> INFO: ROC 7 VthrComp = 128
[13:23:06.704] <TB0> INFO: ROC 8 VthrComp = 133
[13:23:06.704] <TB0> INFO: ROC 9 VthrComp = 131
[13:23:06.704] <TB0> INFO: ROC 10 VthrComp = 128
[13:23:06.704] <TB0> INFO: ROC 11 VthrComp = 125
[13:23:06.704] <TB0> INFO: ROC 12 VthrComp = 113
[13:23:06.704] <TB0> INFO: ROC 13 VthrComp = 120
[13:23:06.704] <TB0> INFO: ROC 14 VthrComp = 126
[13:23:06.704] <TB0> INFO: ROC 15 VthrComp = 126
[13:23:06.986] <TB0> INFO: Expecting 41600 events.
[13:23:10.559] <TB0> INFO: 41600 events read in total (2982ms).
[13:23:10.560] <TB0> INFO: Test took 3854ms.
[13:23:10.569] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[13:23:10.569] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[13:23:10.580] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:23:10.580] <TB0> INFO: run 1 of 1
[13:23:10.858] <TB0> INFO: Expecting 5025280 events.
[13:23:37.886] <TB0> INFO: 590536 events read in total (26437ms).
[13:24:04.026] <TB0> INFO: 1179360 events read in total (52577ms).
[13:24:30.040] <TB0> INFO: 1768392 events read in total (78591ms).
[13:24:56.062] <TB0> INFO: 2357632 events read in total (104613ms).
[13:25:22.070] <TB0> INFO: 2945072 events read in total (130621ms).
[13:25:48.198] <TB0> INFO: 3531184 events read in total (156749ms).
[13:26:14.245] <TB0> INFO: 4116936 events read in total (182796ms).
[13:26:40.505] <TB0> INFO: 4702568 events read in total (209056ms).
[13:26:55.049] <TB0> INFO: 5025280 events read in total (223600ms).
[13:26:55.162] <TB0> INFO: Test took 224582ms.
[13:27:21.516] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 63.0336 for pixel 0/22 mean/min/max = 47.4518/31.4644/63.4392
[13:27:21.516] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 61.0716 for pixel 6/5 mean/min/max = 46.8308/32.5373/61.1242
[13:27:21.517] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 61.9938 for pixel 1/75 mean/min/max = 47.5085/32.8322/62.1848
[13:27:21.517] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 59.0884 for pixel 15/1 mean/min/max = 46.1482/33.0842/59.2122
[13:27:21.518] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 61.5124 for pixel 16/70 mean/min/max = 46.4053/31.2763/61.5343
[13:27:21.518] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 66.4819 for pixel 0/3 mean/min/max = 50.4099/34.2661/66.5538
[13:27:21.519] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 62.9035 for pixel 15/3 mean/min/max = 47.2933/31.6116/62.975
[13:27:21.519] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 60.0482 for pixel 0/10 mean/min/max = 46.0647/32.081/60.0483
[13:27:21.520] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 61.4414 for pixel 1/16 mean/min/max = 47.2179/32.9626/61.4731
[13:27:21.520] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 63.2084 for pixel 5/14 mean/min/max = 48.0948/32.8786/63.3109
[13:27:21.521] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 64.9204 for pixel 0/14 mean/min/max = 48.4678/31.7296/65.206
[13:27:21.521] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 69.1104 for pixel 19/4 mean/min/max = 50.8081/32.4603/69.1559
[13:27:21.522] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 62.9105 for pixel 15/4 mean/min/max = 47.758/32.5066/63.0095
[13:27:21.522] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 61.5026 for pixel 7/23 mean/min/max = 47.2612/32.9351/61.5872
[13:27:21.522] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 59.8463 for pixel 6/78 mean/min/max = 45.9082/31.7805/60.0358
[13:27:21.523] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 58.4253 for pixel 22/0 mean/min/max = 45.0056/31.5075/58.5038
[13:27:21.526] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[13:27:21.615] <TB0> INFO: Expecting 411648 events.
[13:27:31.210] <TB0> INFO: 411648 events read in total (9004ms).
[13:27:31.219] <TB0> INFO: Expecting 411648 events.
[13:27:40.374] <TB0> INFO: 411648 events read in total (8751ms).
[13:27:40.384] <TB0> INFO: Expecting 411648 events.
[13:27:49.580] <TB0> INFO: 411648 events read in total (8793ms).
[13:27:49.597] <TB0> INFO: Expecting 411648 events.
[13:27:58.900] <TB0> INFO: 411648 events read in total (8900ms).
[13:27:58.916] <TB0> INFO: Expecting 411648 events.
[13:28:08.242] <TB0> INFO: 411648 events read in total (8923ms).
[13:28:08.265] <TB0> INFO: Expecting 411648 events.
[13:28:17.578] <TB0> INFO: 411648 events read in total (8910ms).
[13:28:17.599] <TB0> INFO: Expecting 411648 events.
[13:28:26.795] <TB0> INFO: 411648 events read in total (8793ms).
[13:28:26.822] <TB0> INFO: Expecting 411648 events.
[13:28:36.061] <TB0> INFO: 411648 events read in total (8836ms).
[13:28:36.087] <TB0> INFO: Expecting 411648 events.
[13:28:45.378] <TB0> INFO: 411648 events read in total (8888ms).
[13:28:45.412] <TB0> INFO: Expecting 411648 events.
[13:28:54.801] <TB0> INFO: 411648 events read in total (8986ms).
[13:28:54.842] <TB0> INFO: Expecting 411648 events.
[13:29:04.177] <TB0> INFO: 411648 events read in total (8931ms).
[13:29:04.228] <TB0> INFO: Expecting 411648 events.
[13:29:13.621] <TB0> INFO: 411648 events read in total (8990ms).
[13:29:13.676] <TB0> INFO: Expecting 411648 events.
[13:29:23.061] <TB0> INFO: 411648 events read in total (8982ms).
[13:29:23.129] <TB0> INFO: Expecting 411648 events.
[13:29:32.395] <TB0> INFO: 411648 events read in total (8863ms).
[13:29:32.451] <TB0> INFO: Expecting 411648 events.
[13:29:41.738] <TB0> INFO: 411648 events read in total (8884ms).
[13:29:41.818] <TB0> INFO: Expecting 411648 events.
[13:29:51.212] <TB0> INFO: 411648 events read in total (8990ms).
[13:29:51.279] <TB0> INFO: Test took 149753ms.
[13:29:51.998] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[13:29:52.011] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:29:52.011] <TB0> INFO: run 1 of 1
[13:29:52.249] <TB0> INFO: Expecting 5025280 events.
[13:30:19.014] <TB0> INFO: 592784 events read in total (26173ms).
[13:30:45.308] <TB0> INFO: 1183176 events read in total (52467ms).
[13:31:11.593] <TB0> INFO: 1773512 events read in total (78752ms).
[13:31:38.179] <TB0> INFO: 2363816 events read in total (105338ms).
[13:32:04.570] <TB0> INFO: 2955568 events read in total (131729ms).
[13:32:31.272] <TB0> INFO: 3547600 events read in total (158431ms).
[13:32:58.196] <TB0> INFO: 4139584 events read in total (185355ms).
[13:33:24.655] <TB0> INFO: 4730760 events read in total (211815ms).
[13:33:38.225] <TB0> INFO: 5025280 events read in total (225384ms).
[13:33:38.428] <TB0> INFO: Test took 226418ms.
[13:34:03.625] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 9.948956 .. 146.336914
[13:34:03.866] <TB0> INFO: Expecting 208000 events.
[13:34:14.390] <TB0> INFO: 208000 events read in total (9932ms).
[13:34:14.392] <TB0> INFO: Test took 10764ms.
[13:34:14.442] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 9 .. 156 (-1/-1) hits flags = 528 (plus default)
[13:34:14.456] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:34:14.456] <TB0> INFO: run 1 of 1
[13:34:14.734] <TB0> INFO: Expecting 4925440 events.
[13:34:41.325] <TB0> INFO: 574408 events read in total (25999ms).
[13:35:07.358] <TB0> INFO: 1148000 events read in total (52034ms).
[13:35:33.370] <TB0> INFO: 1722016 events read in total (78044ms).
[13:35:59.441] <TB0> INFO: 2295992 events read in total (104115ms).
[13:36:25.506] <TB0> INFO: 2869240 events read in total (130181ms).
[13:36:51.386] <TB0> INFO: 3442280 events read in total (156060ms).
[13:37:17.521] <TB0> INFO: 4015400 events read in total (182195ms).
[13:37:43.397] <TB0> INFO: 4587976 events read in total (208071ms).
[13:37:59.134] <TB0> INFO: 4925440 events read in total (223808ms).
[13:37:59.279] <TB0> INFO: Test took 224824ms.
[13:38:26.281] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 26.714442 .. 52.152806
[13:38:26.537] <TB0> INFO: Expecting 208000 events.
[13:38:36.601] <TB0> INFO: 208000 events read in total (9473ms).
[13:38:36.602] <TB0> INFO: Test took 10318ms.
[13:38:36.650] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 16 .. 62 (-1/-1) hits flags = 528 (plus default)
[13:38:36.664] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:38:36.664] <TB0> INFO: run 1 of 1
[13:38:36.942] <TB0> INFO: Expecting 1564160 events.
[13:39:05.526] <TB0> INFO: 641488 events read in total (27993ms).
[13:39:33.367] <TB0> INFO: 1280520 events read in total (55835ms).
[13:39:45.407] <TB0> INFO: 1564160 events read in total (67874ms).
[13:39:45.451] <TB0> INFO: Test took 68788ms.
[13:40:00.160] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 27.700045 .. 52.383171
[13:40:00.408] <TB0> INFO: Expecting 208000 events.
[13:40:10.280] <TB0> INFO: 208000 events read in total (9279ms).
[13:40:10.281] <TB0> INFO: Test took 10120ms.
[13:40:10.330] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 17 .. 62 (-1/-1) hits flags = 528 (plus default)
[13:40:10.343] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:40:10.343] <TB0> INFO: run 1 of 1
[13:40:10.621] <TB0> INFO: Expecting 1530880 events.
[13:40:38.757] <TB0> INFO: 636904 events read in total (27545ms).
[13:41:06.064] <TB0> INFO: 1273056 events read in total (54852ms).
[13:41:17.615] <TB0> INFO: 1530880 events read in total (66404ms).
[13:41:17.657] <TB0> INFO: Test took 67315ms.
[13:41:33.214] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 24.859074 .. 49.686497
[13:41:33.502] <TB0> INFO: Expecting 208000 events.
[13:41:44.297] <TB0> INFO: 208000 events read in total (10203ms).
[13:41:44.298] <TB0> INFO: Test took 11083ms.
[13:41:44.378] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 14 .. 59 (-1/-1) hits flags = 528 (plus default)
[13:41:44.392] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:41:44.392] <TB0> INFO: run 1 of 1
[13:41:44.716] <TB0> INFO: Expecting 1530880 events.
[13:42:12.982] <TB0> INFO: 656840 events read in total (27674ms).
[13:42:40.383] <TB0> INFO: 1313448 events read in total (55075ms).
[13:42:50.042] <TB0> INFO: 1530880 events read in total (64734ms).
[13:42:50.089] <TB0> INFO: Test took 65698ms.
[13:43:06.448] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[13:43:06.448] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 15 .. 55 (-1/-1) hits flags = 528 (plus default)
[13:43:06.461] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[13:43:06.462] <TB0> INFO: run 1 of 1
[13:43:06.720] <TB0> INFO: Expecting 1364480 events.
[13:43:35.879] <TB0> INFO: 668664 events read in total (28567ms).
[13:44:03.757] <TB0> INFO: 1336616 events read in total (56445ms).
[13:44:05.364] <TB0> INFO: 1364480 events read in total (58052ms).
[13:44:05.396] <TB0> INFO: Test took 58935ms.
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C0.dat
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C1.dat
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C2.dat
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C3.dat
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C4.dat
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C5.dat
[13:44:20.094] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C6.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C7.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C8.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C9.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C10.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C11.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C12.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C13.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C14.dat
[13:44:20.095] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C15.dat
[13:44:20.095] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C0.dat
[13:44:20.101] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C1.dat
[13:44:20.105] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C2.dat
[13:44:20.110] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C3.dat
[13:44:20.116] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C4.dat
[13:44:20.122] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C5.dat
[13:44:20.129] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C6.dat
[13:44:20.135] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C7.dat
[13:44:20.142] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C8.dat
[13:44:20.148] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C9.dat
[13:44:20.154] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C10.dat
[13:44:20.160] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C11.dat
[13:44:20.166] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C12.dat
[13:44:20.170] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C13.dat
[13:44:20.175] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C14.dat
[13:44:20.180] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters35_C15.dat
[13:44:20.184] <TB0> INFO: PixTestTrim::trimTest() done
[13:44:20.184] <TB0> INFO: vtrim: 135 112 128 122 137 131 151 117 133 142 118 149 122 135 121 135
[13:44:20.184] <TB0> INFO: vthrcomp: 127 126 122 113 119 111 130 128 133 131 128 125 113 120 126 126
[13:44:20.185] <TB0> INFO: vcal mean: 35.27 35.03 35.12 34.95 34.99 35.39 35.15 34.98 35.18 35.02 35.53 37.54 35.16 34.99 34.96 34.99
[13:44:20.185] <TB0> INFO: vcal RMS: 1.59 1.11 1.18 1.02 1.20 1.49 1.29 1.05 1.30 1.12 1.77 3.11 1.36 1.12 1.00 1.01
[13:44:20.185] <TB0> INFO: bits mean: 9.45 8.80 9.00 9.30 9.86 8.27 10.06 9.07 8.97 8.90 9.02 10.06 9.39 9.50 9.49 10.04
[13:44:20.185] <TB0> INFO: bits RMS: 2.82 2.96 2.76 2.67 2.64 2.80 2.43 2.89 2.78 2.72 2.94 2.59 2.68 2.53 2.75 2.59
[13:44:20.192] <TB0> INFO: ----------------------------------------------------------------------
[13:44:20.192] <TB0> INFO: PixTestTrim::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[13:44:20.192] <TB0> INFO: ----------------------------------------------------------------------
[13:44:20.195] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[13:44:20.207] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:44:20.207] <TB0> INFO: run 1 of 1
[13:44:20.477] <TB0> INFO: Expecting 4160000 events.
[13:44:54.807] <TB0> INFO: 774855 events read in total (33736ms).
[13:45:27.652] <TB0> INFO: 1541940 events read in total (66581ms).
[13:46:00.225] <TB0> INFO: 2302930 events read in total (99154ms).
[13:46:32.911] <TB0> INFO: 3060115 events read in total (131840ms).
[13:47:05.415] <TB0> INFO: 3812995 events read in total (164344ms).
[13:47:20.363] <TB0> INFO: 4160000 events read in total (179292ms).
[13:47:20.465] <TB0> INFO: Test took 180258ms.
[13:47:53.160] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 219 (-1/-1) hits flags = 528 (plus default)
[13:47:53.173] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:47:53.173] <TB0> INFO: run 1 of 1
[13:47:53.410] <TB0> INFO: Expecting 4576000 events.
[13:48:25.603] <TB0> INFO: 722555 events read in total (31601ms).
[13:48:57.144] <TB0> INFO: 1439470 events read in total (63142ms).
[13:49:28.517] <TB0> INFO: 2152900 events read in total (94515ms).
[13:50:00.017] <TB0> INFO: 2863600 events read in total (126015ms).
[13:50:31.512] <TB0> INFO: 3571510 events read in total (157510ms).
[13:51:02.975] <TB0> INFO: 4277125 events read in total (188973ms).
[13:51:16.287] <TB0> INFO: 4576000 events read in total (202285ms).
[13:51:16.388] <TB0> INFO: Test took 203215ms.
[13:51:47.896] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[13:51:47.910] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:51:47.910] <TB0> INFO: run 1 of 1
[13:51:48.207] <TB0> INFO: Expecting 4305600 events.
[13:52:20.408] <TB0> INFO: 739160 events read in total (31608ms).
[13:52:52.099] <TB0> INFO: 1472200 events read in total (63299ms).
[13:53:23.843] <TB0> INFO: 2201715 events read in total (95043ms).
[13:53:55.749] <TB0> INFO: 2927600 events read in total (126949ms).
[13:54:27.213] <TB0> INFO: 3648405 events read in total (158413ms).
[13:54:56.067] <TB0> INFO: 4305600 events read in total (187267ms).
[13:54:56.147] <TB0> INFO: Test took 188238ms.
[13:55:25.776] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 204 (-1/-1) hits flags = 528 (plus default)
[13:55:25.790] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:55:25.790] <TB0> INFO: run 1 of 1
[13:55:26.034] <TB0> INFO: Expecting 4264000 events.
[13:55:58.401] <TB0> INFO: 741975 events read in total (31775ms).
[13:56:30.273] <TB0> INFO: 1477415 events read in total (63647ms).
[13:57:02.629] <TB0> INFO: 2209775 events read in total (96004ms).
[13:57:34.761] <TB0> INFO: 2938040 events read in total (128135ms).
[13:58:06.508] <TB0> INFO: 3662080 events read in total (159882ms).
[13:58:32.677] <TB0> INFO: 4264000 events read in total (186051ms).
[13:58:32.784] <TB0> INFO: Test took 186994ms.
[13:59:01.409] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[13:59:01.422] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[13:59:01.422] <TB0> INFO: run 1 of 1
[13:59:01.669] <TB0> INFO: Expecting 4326400 events.
[13:59:34.009] <TB0> INFO: 737990 events read in total (31749ms).
[14:00:05.606] <TB0> INFO: 1469730 events read in total (63346ms).
[14:00:37.355] <TB0> INFO: 2198330 events read in total (95095ms).
[14:01:09.660] <TB0> INFO: 2923325 events read in total (127400ms).
[14:01:41.205] <TB0> INFO: 3643895 events read in total (158945ms).
[14:02:10.966] <TB0> INFO: 4326400 events read in total (188706ms).
[14:02:11.047] <TB0> INFO: Test took 189625ms.
[14:02:37.722] <TB0> INFO: PixTestTrim::trimBitTest() done
[14:02:37.724] <TB0> INFO: PixTestTrim::doTest() done, duration: 2577 seconds
[14:02:37.724] <TB0> INFO: Decoding statistics:
[14:02:37.724] <TB0> INFO: General information:
[14:02:37.724] <TB0> INFO: 16bit words read: 0
[14:02:37.724] <TB0> INFO: valid events total: 0
[14:02:37.724] <TB0> INFO: empty events: 0
[14:02:37.724] <TB0> INFO: valid events with pixels: 0
[14:02:37.724] <TB0> INFO: valid pixel hits: 0
[14:02:37.724] <TB0> INFO: Event errors: 0
[14:02:37.724] <TB0> INFO: start marker: 0
[14:02:37.724] <TB0> INFO: stop marker: 0
[14:02:37.724] <TB0> INFO: overflow: 0
[14:02:37.724] <TB0> INFO: invalid 5bit words: 0
[14:02:37.724] <TB0> INFO: invalid XOR eye diagram: 0
[14:02:37.724] <TB0> INFO: frame (failed synchr.): 0
[14:02:37.724] <TB0> INFO: idle data (no TBM trl): 0
[14:02:37.724] <TB0> INFO: no data (only TBM hdr): 0
[14:02:37.724] <TB0> INFO: TBM errors: 0
[14:02:37.724] <TB0> INFO: flawed TBM headers: 0
[14:02:37.724] <TB0> INFO: flawed TBM trailers: 0
[14:02:37.724] <TB0> INFO: event ID mismatches: 0
[14:02:37.724] <TB0> INFO: ROC errors: 0
[14:02:37.724] <TB0> INFO: missing ROC header(s): 0
[14:02:37.724] <TB0> INFO: misplaced readback start: 0
[14:02:37.724] <TB0> INFO: Pixel decoding errors: 0
[14:02:37.724] <TB0> INFO: pixel data incomplete: 0
[14:02:37.724] <TB0> INFO: pixel address: 0
[14:02:37.724] <TB0> INFO: pulse height fill bit: 0
[14:02:37.724] <TB0> INFO: buffer corruption: 0
[14:02:38.473] <TB0> INFO: ######################################################################
[14:02:38.473] <TB0> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[14:02:38.473] <TB0> INFO: ######################################################################
[14:02:38.712] <TB0> INFO: Expecting 41600 events.
[14:02:42.161] <TB0> INFO: 41600 events read in total (2857ms).
[14:02:42.162] <TB0> INFO: Test took 3688ms.
[14:02:42.611] <TB0> INFO: Expecting 41600 events.
[14:02:46.169] <TB0> INFO: 41600 events read in total (2966ms).
[14:02:46.170] <TB0> INFO: Test took 3802ms.
[14:02:46.461] <TB0> INFO: Expecting 41600 events.
[14:02:50.030] <TB0> INFO: 41600 events read in total (2977ms).
[14:02:50.032] <TB0> INFO: Test took 3837ms.
[14:02:50.336] <TB0> INFO: Expecting 41600 events.
[14:02:53.853] <TB0> INFO: 41600 events read in total (2925ms).
[14:02:53.854] <TB0> INFO: Test took 3798ms.
[14:02:54.144] <TB0> INFO: Expecting 41600 events.
[14:02:57.725] <TB0> INFO: 41600 events read in total (2989ms).
[14:02:57.726] <TB0> INFO: Test took 3848ms.
[14:02:58.018] <TB0> INFO: Expecting 41600 events.
[14:03:01.584] <TB0> INFO: 41600 events read in total (2975ms).
[14:03:01.585] <TB0> INFO: Test took 3833ms.
[14:03:01.875] <TB0> INFO: Expecting 41600 events.
[14:03:05.480] <TB0> INFO: 41600 events read in total (3013ms).
[14:03:05.481] <TB0> INFO: Test took 3872ms.
[14:03:05.771] <TB0> INFO: Expecting 41600 events.
[14:03:09.408] <TB0> INFO: 41600 events read in total (3045ms).
[14:03:09.409] <TB0> INFO: Test took 3903ms.
[14:03:09.700] <TB0> INFO: Expecting 41600 events.
[14:03:13.346] <TB0> INFO: 41600 events read in total (3055ms).
[14:03:13.347] <TB0> INFO: Test took 3913ms.
[14:03:13.640] <TB0> INFO: Expecting 41600 events.
[14:03:17.176] <TB0> INFO: 41600 events read in total (2944ms).
[14:03:17.177] <TB0> INFO: Test took 3803ms.
[14:03:17.469] <TB0> INFO: Expecting 41600 events.
[14:03:21.015] <TB0> INFO: 41600 events read in total (2954ms).
[14:03:21.016] <TB0> INFO: Test took 3812ms.
[14:03:21.305] <TB0> INFO: Expecting 41600 events.
[14:03:24.856] <TB0> INFO: 41600 events read in total (2959ms).
[14:03:24.857] <TB0> INFO: Test took 3817ms.
[14:03:25.147] <TB0> INFO: Expecting 41600 events.
[14:03:28.655] <TB0> INFO: 41600 events read in total (2916ms).
[14:03:28.656] <TB0> INFO: Test took 3774ms.
[14:03:28.946] <TB0> INFO: Expecting 41600 events.
[14:03:32.465] <TB0> INFO: 41600 events read in total (2927ms).
[14:03:32.466] <TB0> INFO: Test took 3785ms.
[14:03:32.756] <TB0> INFO: Expecting 41600 events.
[14:03:36.310] <TB0> INFO: 41600 events read in total (2963ms).
[14:03:36.311] <TB0> INFO: Test took 3821ms.
[14:03:36.602] <TB0> INFO: Expecting 41600 events.
[14:03:40.244] <TB0> INFO: 41600 events read in total (3050ms).
[14:03:40.245] <TB0> INFO: Test took 3909ms.
[14:03:40.535] <TB0> INFO: Expecting 41600 events.
[14:03:44.040] <TB0> INFO: 41600 events read in total (2913ms).
[14:03:44.041] <TB0> INFO: Test took 3771ms.
[14:03:44.331] <TB0> INFO: Expecting 41600 events.
[14:03:47.844] <TB0> INFO: 41600 events read in total (2922ms).
[14:03:47.845] <TB0> INFO: Test took 3780ms.
[14:03:48.137] <TB0> INFO: Expecting 41600 events.
[14:03:51.712] <TB0> INFO: 41600 events read in total (2983ms).
[14:03:51.713] <TB0> INFO: Test took 3841ms.
[14:03:52.005] <TB0> INFO: Expecting 41600 events.
[14:03:55.564] <TB0> INFO: 41600 events read in total (2967ms).
[14:03:55.565] <TB0> INFO: Test took 3828ms.
[14:03:55.855] <TB0> INFO: Expecting 41600 events.
[14:03:59.430] <TB0> INFO: 41600 events read in total (2983ms).
[14:03:59.431] <TB0> INFO: Test took 3842ms.
[14:03:59.753] <TB0> INFO: Expecting 41600 events.
[14:04:03.459] <TB0> INFO: 41600 events read in total (3114ms).
[14:04:03.460] <TB0> INFO: Test took 4002ms.
[14:04:03.750] <TB0> INFO: Expecting 41600 events.
[14:04:07.517] <TB0> INFO: 41600 events read in total (3175ms).
[14:04:07.518] <TB0> INFO: Test took 4033ms.
[14:04:07.811] <TB0> INFO: Expecting 41600 events.
[14:04:11.381] <TB0> INFO: 41600 events read in total (2977ms).
[14:04:11.382] <TB0> INFO: Test took 3837ms.
[14:04:11.671] <TB0> INFO: Expecting 41600 events.
[14:04:15.245] <TB0> INFO: 41600 events read in total (2982ms).
[14:04:15.246] <TB0> INFO: Test took 3840ms.
[14:04:15.538] <TB0> INFO: Expecting 41600 events.
[14:04:19.073] <TB0> INFO: 41600 events read in total (2943ms).
[14:04:19.074] <TB0> INFO: Test took 3802ms.
[14:04:19.365] <TB0> INFO: Expecting 2560 events.
[14:04:20.250] <TB0> INFO: 2560 events read in total (294ms).
[14:04:20.251] <TB0> INFO: Test took 1163ms.
[14:04:20.560] <TB0> INFO: Expecting 2560 events.
[14:04:21.452] <TB0> INFO: 2560 events read in total (301ms).
[14:04:21.452] <TB0> INFO: Test took 1201ms.
[14:04:21.760] <TB0> INFO: Expecting 2560 events.
[14:04:22.650] <TB0> INFO: 2560 events read in total (298ms).
[14:04:22.650] <TB0> INFO: Test took 1197ms.
[14:04:22.958] <TB0> INFO: Expecting 2560 events.
[14:04:23.842] <TB0> INFO: 2560 events read in total (293ms).
[14:04:23.842] <TB0> INFO: Test took 1192ms.
[14:04:24.150] <TB0> INFO: Expecting 2560 events.
[14:04:25.030] <TB0> INFO: 2560 events read in total (289ms).
[14:04:25.030] <TB0> INFO: Test took 1187ms.
[14:04:25.337] <TB0> INFO: Expecting 2560 events.
[14:04:26.217] <TB0> INFO: 2560 events read in total (288ms).
[14:04:26.217] <TB0> INFO: Test took 1186ms.
[14:04:26.525] <TB0> INFO: Expecting 2560 events.
[14:04:27.404] <TB0> INFO: 2560 events read in total (287ms).
[14:04:27.404] <TB0> INFO: Test took 1187ms.
[14:04:27.713] <TB0> INFO: Expecting 2560 events.
[14:04:28.600] <TB0> INFO: 2560 events read in total (295ms).
[14:04:28.601] <TB0> INFO: Test took 1196ms.
[14:04:28.907] <TB0> INFO: Expecting 2560 events.
[14:04:29.797] <TB0> INFO: 2560 events read in total (298ms).
[14:04:29.798] <TB0> INFO: Test took 1196ms.
[14:04:30.105] <TB0> INFO: Expecting 2560 events.
[14:04:30.989] <TB0> INFO: 2560 events read in total (293ms).
[14:04:30.989] <TB0> INFO: Test took 1191ms.
[14:04:31.297] <TB0> INFO: Expecting 2560 events.
[14:04:32.185] <TB0> INFO: 2560 events read in total (296ms).
[14:04:32.185] <TB0> INFO: Test took 1195ms.
[14:04:32.494] <TB0> INFO: Expecting 2560 events.
[14:04:33.376] <TB0> INFO: 2560 events read in total (290ms).
[14:04:33.376] <TB0> INFO: Test took 1190ms.
[14:04:33.684] <TB0> INFO: Expecting 2560 events.
[14:04:34.570] <TB0> INFO: 2560 events read in total (295ms).
[14:04:34.570] <TB0> INFO: Test took 1193ms.
[14:04:34.878] <TB0> INFO: Expecting 2560 events.
[14:04:35.764] <TB0> INFO: 2560 events read in total (294ms).
[14:04:35.764] <TB0> INFO: Test took 1193ms.
[14:04:36.071] <TB0> INFO: Expecting 2560 events.
[14:04:36.964] <TB0> INFO: 2560 events read in total (301ms).
[14:04:36.965] <TB0> INFO: Test took 1200ms.
[14:04:37.272] <TB0> INFO: Expecting 2560 events.
[14:04:38.166] <TB0> INFO: 2560 events read in total (302ms).
[14:04:38.166] <TB0> INFO: Test took 1201ms.
[14:04:38.170] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:04:38.476] <TB0> INFO: Expecting 655360 events.
[14:04:53.443] <TB0> INFO: 655360 events read in total (14375ms).
[14:04:53.456] <TB0> INFO: Expecting 655360 events.
[14:05:08.043] <TB0> INFO: 655360 events read in total (14184ms).
[14:05:08.064] <TB0> INFO: Expecting 655360 events.
[14:05:22.739] <TB0> INFO: 655360 events read in total (14272ms).
[14:05:22.769] <TB0> INFO: Expecting 655360 events.
[14:05:37.335] <TB0> INFO: 655360 events read in total (14163ms).
[14:05:37.370] <TB0> INFO: Expecting 655360 events.
[14:05:51.891] <TB0> INFO: 655360 events read in total (14118ms).
[14:05:51.922] <TB0> INFO: Expecting 655360 events.
[14:06:06.606] <TB0> INFO: 655360 events read in total (14281ms).
[14:06:06.641] <TB0> INFO: Expecting 655360 events.
[14:06:21.223] <TB0> INFO: 655360 events read in total (14178ms).
[14:06:21.262] <TB0> INFO: Expecting 655360 events.
[14:06:35.885] <TB0> INFO: 655360 events read in total (14219ms).
[14:06:35.930] <TB0> INFO: Expecting 655360 events.
[14:06:50.534] <TB0> INFO: 655360 events read in total (14201ms).
[14:06:50.584] <TB0> INFO: Expecting 655360 events.
[14:07:05.268] <TB0> INFO: 655360 events read in total (14281ms).
[14:07:05.331] <TB0> INFO: Expecting 655360 events.
[14:07:19.998] <TB0> INFO: 655360 events read in total (14264ms).
[14:07:20.093] <TB0> INFO: Expecting 655360 events.
[14:07:34.729] <TB0> INFO: 655360 events read in total (14233ms).
[14:07:34.806] <TB0> INFO: Expecting 655360 events.
[14:07:49.448] <TB0> INFO: 655360 events read in total (14238ms).
[14:07:49.539] <TB0> INFO: Expecting 655360 events.
[14:08:04.310] <TB0> INFO: 655360 events read in total (14368ms).
[14:08:04.400] <TB0> INFO: Expecting 655360 events.
[14:08:19.156] <TB0> INFO: 655360 events read in total (14353ms).
[14:08:19.248] <TB0> INFO: Expecting 655360 events.
[14:08:33.990] <TB0> INFO: 655360 events read in total (14338ms).
[14:08:34.095] <TB0> INFO: Test took 235925ms.
[14:08:34.195] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:08:34.449] <TB0> INFO: Expecting 655360 events.
[14:08:49.119] <TB0> INFO: 655360 events read in total (14078ms).
[14:08:49.134] <TB0> INFO: Expecting 655360 events.
[14:09:03.684] <TB0> INFO: 655360 events read in total (14147ms).
[14:09:03.702] <TB0> INFO: Expecting 655360 events.
[14:09:18.308] <TB0> INFO: 655360 events read in total (14202ms).
[14:09:18.338] <TB0> INFO: Expecting 655360 events.
[14:09:33.180] <TB0> INFO: 655360 events read in total (14439ms).
[14:09:33.208] <TB0> INFO: Expecting 655360 events.
[14:09:47.659] <TB0> INFO: 655360 events read in total (14048ms).
[14:09:47.700] <TB0> INFO: Expecting 655360 events.
[14:10:02.379] <TB0> INFO: 655360 events read in total (14276ms).
[14:10:02.421] <TB0> INFO: Expecting 655360 events.
[14:10:16.869] <TB0> INFO: 655360 events read in total (14045ms).
[14:10:16.914] <TB0> INFO: Expecting 655360 events.
[14:10:31.736] <TB0> INFO: 655360 events read in total (14419ms).
[14:10:31.782] <TB0> INFO: Expecting 655360 events.
[14:10:46.023] <TB0> INFO: 655360 events read in total (13838ms).
[14:10:46.070] <TB0> INFO: Expecting 655360 events.
[14:11:00.632] <TB0> INFO: 655360 events read in total (14159ms).
[14:11:00.726] <TB0> INFO: Expecting 655360 events.
[14:11:15.429] <TB0> INFO: 655360 events read in total (14299ms).
[14:11:15.557] <TB0> INFO: Expecting 655360 events.
[14:11:30.300] <TB0> INFO: 655360 events read in total (14340ms).
[14:11:30.422] <TB0> INFO: Expecting 655360 events.
[14:11:45.184] <TB0> INFO: 655360 events read in total (14359ms).
[14:11:45.274] <TB0> INFO: Expecting 655360 events.
[14:12:00.093] <TB0> INFO: 655360 events read in total (14416ms).
[14:12:00.190] <TB0> INFO: Expecting 655360 events.
[14:12:15.070] <TB0> INFO: 655360 events read in total (14477ms).
[14:12:15.178] <TB0> INFO: Expecting 655360 events.
[14:12:29.709] <TB0> INFO: 655360 events read in total (14128ms).
[14:12:29.817] <TB0> INFO: Test took 235622ms.
[14:12:30.012] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.018] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.024] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.030] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.035] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.041] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.047] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.053] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.059] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:30.065] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:30.070] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.077] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:30.082] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:30.088] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:30.094] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.100] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:30.106] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:30.112] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:30.118] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:30.124] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[14:12:30.130] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.136] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:30.142] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:30.149] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:30.154] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:30.161] <TB0> INFO: safety margin for low PH: adding 5, margin is now 25
[14:12:30.167] <TB0> INFO: safety margin for low PH: adding 6, margin is now 26
[14:12:30.173] <TB0> INFO: safety margin for low PH: adding 7, margin is now 27
[14:12:30.179] <TB0> INFO: safety margin for low PH: adding 8, margin is now 28
[14:12:30.185] <TB0> INFO: safety margin for low PH: adding 9, margin is now 29
[14:12:30.191] <TB0> INFO: safety margin for low PH: adding 10, margin is now 30
[14:12:30.198] <TB0> INFO: safety margin for low PH: adding 11, margin is now 31
[14:12:30.203] <TB0> INFO: safety margin for low PH: adding 12, margin is now 32
[14:12:30.210] <TB0> INFO: safety margin for low PH: adding 13, margin is now 33
[14:12:30.216] <TB0> INFO: safety margin for low PH: adding 14, margin is now 34
[14:12:30.222] <TB0> INFO: safety margin for low PH: adding 15, margin is now 35
[14:12:30.229] <TB0> INFO: safety margin for low PH: adding 16, margin is now 36
[14:12:30.235] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.241] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:30.247] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:30.253] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:30.259] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.265] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.270] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.276] <TB0> INFO: safety margin for low PH: adding 0, margin is now 20
[14:12:30.281] <TB0> INFO: safety margin for low PH: adding 1, margin is now 21
[14:12:30.287] <TB0> INFO: safety margin for low PH: adding 2, margin is now 22
[14:12:30.293] <TB0> INFO: safety margin for low PH: adding 3, margin is now 23
[14:12:30.299] <TB0> INFO: safety margin for low PH: adding 4, margin is now 24
[14:12:30.333] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C0.dat
[14:12:30.333] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C1.dat
[14:12:30.333] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C2.dat
[14:12:30.333] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C3.dat
[14:12:30.333] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C4.dat
[14:12:30.334] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C5.dat
[14:12:30.334] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C6.dat
[14:12:30.334] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C7.dat
[14:12:30.334] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C8.dat
[14:12:30.334] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C9.dat
[14:12:30.334] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C10.dat
[14:12:30.335] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C11.dat
[14:12:30.335] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C12.dat
[14:12:30.335] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C13.dat
[14:12:30.335] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C14.dat
[14:12:30.335] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters35_C15.dat
[14:12:30.586] <TB0> INFO: Expecting 41600 events.
[14:12:33.782] <TB0> INFO: 41600 events read in total (2604ms).
[14:12:33.783] <TB0> INFO: Test took 3444ms.
[14:12:34.234] <TB0> INFO: Expecting 41600 events.
[14:12:37.274] <TB0> INFO: 41600 events read in total (2448ms).
[14:12:37.275] <TB0> INFO: Test took 3281ms.
[14:12:37.730] <TB0> INFO: Expecting 41600 events.
[14:12:40.878] <TB0> INFO: 41600 events read in total (2556ms).
[14:12:40.879] <TB0> INFO: Test took 3390ms.
[14:12:41.096] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:41.185] <TB0> INFO: Expecting 2560 events.
[14:12:42.078] <TB0> INFO: 2560 events read in total (301ms).
[14:12:42.079] <TB0> INFO: Test took 983ms.
[14:12:42.082] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:42.386] <TB0> INFO: Expecting 2560 events.
[14:12:43.282] <TB0> INFO: 2560 events read in total (304ms).
[14:12:43.282] <TB0> INFO: Test took 1200ms.
[14:12:43.285] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:43.590] <TB0> INFO: Expecting 2560 events.
[14:12:44.474] <TB0> INFO: 2560 events read in total (292ms).
[14:12:44.474] <TB0> INFO: Test took 1189ms.
[14:12:44.479] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:44.783] <TB0> INFO: Expecting 2560 events.
[14:12:45.675] <TB0> INFO: 2560 events read in total (300ms).
[14:12:45.675] <TB0> INFO: Test took 1196ms.
[14:12:45.679] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:45.984] <TB0> INFO: Expecting 2560 events.
[14:12:46.882] <TB0> INFO: 2560 events read in total (306ms).
[14:12:46.882] <TB0> INFO: Test took 1203ms.
[14:12:46.886] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:47.190] <TB0> INFO: Expecting 2560 events.
[14:12:48.084] <TB0> INFO: 2560 events read in total (302ms).
[14:12:48.084] <TB0> INFO: Test took 1198ms.
[14:12:48.091] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:48.391] <TB0> INFO: Expecting 2560 events.
[14:12:49.281] <TB0> INFO: 2560 events read in total (298ms).
[14:12:49.282] <TB0> INFO: Test took 1191ms.
[14:12:49.285] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:49.591] <TB0> INFO: Expecting 2560 events.
[14:12:50.487] <TB0> INFO: 2560 events read in total (304ms).
[14:12:50.487] <TB0> INFO: Test took 1202ms.
[14:12:50.491] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:50.796] <TB0> INFO: Expecting 2560 events.
[14:12:51.687] <TB0> INFO: 2560 events read in total (300ms).
[14:12:51.687] <TB0> INFO: Test took 1196ms.
[14:12:51.690] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:51.996] <TB0> INFO: Expecting 2560 events.
[14:12:52.885] <TB0> INFO: 2560 events read in total (297ms).
[14:12:52.886] <TB0> INFO: Test took 1196ms.
[14:12:52.888] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:53.194] <TB0> INFO: Expecting 2560 events.
[14:12:54.075] <TB0> INFO: 2560 events read in total (289ms).
[14:12:54.075] <TB0> INFO: Test took 1187ms.
[14:12:54.078] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:54.384] <TB0> INFO: Expecting 2560 events.
[14:12:55.276] <TB0> INFO: 2560 events read in total (300ms).
[14:12:55.276] <TB0> INFO: Test took 1198ms.
[14:12:55.280] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:55.584] <TB0> INFO: Expecting 2560 events.
[14:12:56.469] <TB0> INFO: 2560 events read in total (293ms).
[14:12:56.469] <TB0> INFO: Test took 1189ms.
[14:12:56.473] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:56.777] <TB0> INFO: Expecting 2560 events.
[14:12:57.664] <TB0> INFO: 2560 events read in total (295ms).
[14:12:57.664] <TB0> INFO: Test took 1191ms.
[14:12:57.666] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:57.972] <TB0> INFO: Expecting 2560 events.
[14:12:58.861] <TB0> INFO: 2560 events read in total (297ms).
[14:12:58.862] <TB0> INFO: Test took 1196ms.
[14:12:58.865] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:12:59.171] <TB0> INFO: Expecting 2560 events.
[14:13:00.064] <TB0> INFO: 2560 events read in total (301ms).
[14:13:00.064] <TB0> INFO: Test took 1199ms.
[14:13:00.067] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:00.374] <TB0> INFO: Expecting 2560 events.
[14:13:01.262] <TB0> INFO: 2560 events read in total (297ms).
[14:13:01.263] <TB0> INFO: Test took 1196ms.
[14:13:01.268] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:01.571] <TB0> INFO: Expecting 2560 events.
[14:13:02.467] <TB0> INFO: 2560 events read in total (304ms).
[14:13:02.467] <TB0> INFO: Test took 1200ms.
[14:13:02.471] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:02.775] <TB0> INFO: Expecting 2560 events.
[14:13:03.668] <TB0> INFO: 2560 events read in total (301ms).
[14:13:03.668] <TB0> INFO: Test took 1197ms.
[14:13:03.671] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:03.978] <TB0> INFO: Expecting 2560 events.
[14:13:04.869] <TB0> INFO: 2560 events read in total (299ms).
[14:13:04.869] <TB0> INFO: Test took 1198ms.
[14:13:04.872] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:05.177] <TB0> INFO: Expecting 2560 events.
[14:13:06.058] <TB0> INFO: 2560 events read in total (289ms).
[14:13:06.058] <TB0> INFO: Test took 1186ms.
[14:13:06.061] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:06.366] <TB0> INFO: Expecting 2560 events.
[14:13:07.254] <TB0> INFO: 2560 events read in total (296ms).
[14:13:07.254] <TB0> INFO: Test took 1194ms.
[14:13:07.257] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:07.563] <TB0> INFO: Expecting 2560 events.
[14:13:08.454] <TB0> INFO: 2560 events read in total (299ms).
[14:13:08.454] <TB0> INFO: Test took 1197ms.
[14:13:08.457] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:08.764] <TB0> INFO: Expecting 2560 events.
[14:13:09.652] <TB0> INFO: 2560 events read in total (296ms).
[14:13:09.652] <TB0> INFO: Test took 1195ms.
[14:13:09.655] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:09.961] <TB0> INFO: Expecting 2560 events.
[14:13:10.853] <TB0> INFO: 2560 events read in total (301ms).
[14:13:10.853] <TB0> INFO: Test took 1198ms.
[14:13:10.856] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:11.162] <TB0> INFO: Expecting 2560 events.
[14:13:12.057] <TB0> INFO: 2560 events read in total (303ms).
[14:13:12.057] <TB0> INFO: Test took 1201ms.
[14:13:12.062] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:12.365] <TB0> INFO: Expecting 2560 events.
[14:13:13.255] <TB0> INFO: 2560 events read in total (298ms).
[14:13:13.255] <TB0> INFO: Test took 1194ms.
[14:13:13.259] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:13.563] <TB0> INFO: Expecting 2560 events.
[14:13:14.451] <TB0> INFO: 2560 events read in total (296ms).
[14:13:14.452] <TB0> INFO: Test took 1193ms.
[14:13:14.455] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:14.758] <TB0> INFO: Expecting 2560 events.
[14:13:15.652] <TB0> INFO: 2560 events read in total (303ms).
[14:13:15.653] <TB0> INFO: Test took 1198ms.
[14:13:15.657] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:15.961] <TB0> INFO: Expecting 2560 events.
[14:13:16.856] <TB0> INFO: 2560 events read in total (303ms).
[14:13:16.857] <TB0> INFO: Test took 1200ms.
[14:13:16.862] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:17.164] <TB0> INFO: Expecting 2560 events.
[14:13:18.063] <TB0> INFO: 2560 events read in total (308ms).
[14:13:18.064] <TB0> INFO: Test took 1203ms.
[14:13:18.067] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:13:18.372] <TB0> INFO: Expecting 2560 events.
[14:13:19.257] <TB0> INFO: 2560 events read in total (294ms).
[14:13:19.257] <TB0> INFO: Test took 1191ms.
[14:13:19.744] <TB0> INFO: PixTestPhOptimization::doTest() done, duration: 641 seconds
[14:13:19.744] <TB0> INFO: PH scale (per ROC): 38 57 40 54 53 52 36 40 50 35 49 33 33 38 44 32
[14:13:19.744] <TB0> INFO: PH offset (per ROC): 111 129 108 126 126 125 101 101 130 85 112 110 111 103 103 98
[14:13:19.754] <TB0> INFO: Decoding statistics:
[14:13:19.754] <TB0> INFO: General information:
[14:13:19.754] <TB0> INFO: 16bit words read: 127888
[14:13:19.754] <TB0> INFO: valid events total: 20480
[14:13:19.755] <TB0> INFO: empty events: 17976
[14:13:19.755] <TB0> INFO: valid events with pixels: 2504
[14:13:19.755] <TB0> INFO: valid pixel hits: 2504
[14:13:19.755] <TB0> INFO: Event errors: 0
[14:13:19.755] <TB0> INFO: start marker: 0
[14:13:19.755] <TB0> INFO: stop marker: 0
[14:13:19.755] <TB0> INFO: overflow: 0
[14:13:19.755] <TB0> INFO: invalid 5bit words: 0
[14:13:19.755] <TB0> INFO: invalid XOR eye diagram: 0
[14:13:19.755] <TB0> INFO: frame (failed synchr.): 0
[14:13:19.755] <TB0> INFO: idle data (no TBM trl): 0
[14:13:19.755] <TB0> INFO: no data (only TBM hdr): 0
[14:13:19.755] <TB0> INFO: TBM errors: 0
[14:13:19.755] <TB0> INFO: flawed TBM headers: 0
[14:13:19.755] <TB0> INFO: flawed TBM trailers: 0
[14:13:19.755] <TB0> INFO: event ID mismatches: 0
[14:13:19.755] <TB0> INFO: ROC errors: 0
[14:13:19.755] <TB0> INFO: missing ROC header(s): 0
[14:13:19.755] <TB0> INFO: misplaced readback start: 0
[14:13:19.755] <TB0> INFO: Pixel decoding errors: 0
[14:13:19.755] <TB0> INFO: pixel data incomplete: 0
[14:13:19.755] <TB0> INFO: pixel address: 0
[14:13:19.755] <TB0> INFO: pulse height fill bit: 0
[14:13:19.755] <TB0> INFO: buffer corruption: 0
[14:13:19.918] <TB0> INFO: ######################################################################
[14:13:19.918] <TB0> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[14:13:19.918] <TB0> INFO: ######################################################################
[14:13:19.932] <TB0> INFO: scanning low vcal = 10
[14:13:20.171] <TB0> INFO: Expecting 41600 events.
[14:13:23.764] <TB0> INFO: 41600 events read in total (3001ms).
[14:13:23.765] <TB0> INFO: Test took 3833ms.
[14:13:23.767] <TB0> INFO: scanning low vcal = 20
[14:13:24.057] <TB0> INFO: Expecting 41600 events.
[14:13:27.653] <TB0> INFO: 41600 events read in total (3004ms).
[14:13:27.653] <TB0> INFO: Test took 3886ms.
[14:13:27.656] <TB0> INFO: scanning low vcal = 30
[14:13:27.949] <TB0> INFO: Expecting 41600 events.
[14:13:31.579] <TB0> INFO: 41600 events read in total (3038ms).
[14:13:31.581] <TB0> INFO: Test took 3925ms.
[14:13:31.584] <TB0> INFO: scanning low vcal = 40
[14:13:31.861] <TB0> INFO: Expecting 41600 events.
[14:13:35.827] <TB0> INFO: 41600 events read in total (3374ms).
[14:13:35.829] <TB0> INFO: Test took 4245ms.
[14:13:35.833] <TB0> INFO: scanning low vcal = 50
[14:13:36.111] <TB0> INFO: Expecting 41600 events.
[14:13:40.071] <TB0> INFO: 41600 events read in total (3369ms).
[14:13:40.073] <TB0> INFO: Test took 4240ms.
[14:13:40.076] <TB0> INFO: scanning low vcal = 60
[14:13:40.372] <TB0> INFO: Expecting 41600 events.
[14:13:44.396] <TB0> INFO: 41600 events read in total (3432ms).
[14:13:44.397] <TB0> INFO: Test took 4319ms.
[14:13:44.401] <TB0> INFO: scanning low vcal = 70
[14:13:44.678] <TB0> INFO: Expecting 41600 events.
[14:13:48.650] <TB0> INFO: 41600 events read in total (3380ms).
[14:13:48.651] <TB0> INFO: Test took 4250ms.
[14:13:48.657] <TB0> INFO: scanning low vcal = 80
[14:13:48.936] <TB0> INFO: Expecting 41600 events.
[14:13:52.915] <TB0> INFO: 41600 events read in total (3387ms).
[14:13:52.916] <TB0> INFO: Test took 4259ms.
[14:13:52.919] <TB0> INFO: scanning low vcal = 90
[14:13:53.196] <TB0> INFO: Expecting 41600 events.
[14:13:57.180] <TB0> INFO: 41600 events read in total (3393ms).
[14:13:57.182] <TB0> INFO: Test took 4261ms.
[14:13:57.186] <TB0> INFO: scanning low vcal = 100
[14:13:57.476] <TB0> INFO: Expecting 41600 events.
[14:14:01.455] <TB0> INFO: 41600 events read in total (3388ms).
[14:14:01.456] <TB0> INFO: Test took 4270ms.
[14:14:01.460] <TB0> INFO: scanning low vcal = 110
[14:14:01.740] <TB0> INFO: Expecting 41600 events.
[14:14:05.785] <TB0> INFO: 41600 events read in total (3453ms).
[14:14:05.786] <TB0> INFO: Test took 4326ms.
[14:14:05.789] <TB0> INFO: scanning low vcal = 120
[14:14:06.066] <TB0> INFO: Expecting 41600 events.
[14:14:10.052] <TB0> INFO: 41600 events read in total (3394ms).
[14:14:10.053] <TB0> INFO: Test took 4264ms.
[14:14:10.056] <TB0> INFO: scanning low vcal = 130
[14:14:10.333] <TB0> INFO: Expecting 41600 events.
[14:14:14.337] <TB0> INFO: 41600 events read in total (3413ms).
[14:14:14.338] <TB0> INFO: Test took 4281ms.
[14:14:14.343] <TB0> INFO: scanning low vcal = 140
[14:14:14.618] <TB0> INFO: Expecting 41600 events.
[14:14:18.574] <TB0> INFO: 41600 events read in total (3364ms).
[14:14:18.575] <TB0> INFO: Test took 4231ms.
[14:14:18.579] <TB0> INFO: scanning low vcal = 150
[14:14:18.855] <TB0> INFO: Expecting 41600 events.
[14:14:22.887] <TB0> INFO: 41600 events read in total (3440ms).
[14:14:22.888] <TB0> INFO: Test took 4309ms.
[14:14:22.897] <TB0> INFO: scanning low vcal = 160
[14:14:23.178] <TB0> INFO: Expecting 41600 events.
[14:14:27.148] <TB0> INFO: 41600 events read in total (3378ms).
[14:14:27.149] <TB0> INFO: Test took 4252ms.
[14:14:27.153] <TB0> INFO: scanning low vcal = 170
[14:14:27.429] <TB0> INFO: Expecting 41600 events.
[14:14:31.370] <TB0> INFO: 41600 events read in total (3349ms).
[14:14:31.371] <TB0> INFO: Test took 4218ms.
[14:14:31.378] <TB0> INFO: scanning low vcal = 180
[14:14:31.650] <TB0> INFO: Expecting 41600 events.
[14:14:35.613] <TB0> INFO: 41600 events read in total (3371ms).
[14:14:35.613] <TB0> INFO: Test took 4235ms.
[14:14:35.618] <TB0> INFO: scanning low vcal = 190
[14:14:35.893] <TB0> INFO: Expecting 41600 events.
[14:14:39.886] <TB0> INFO: 41600 events read in total (3401ms).
[14:14:39.887] <TB0> INFO: Test took 4269ms.
[14:14:39.891] <TB0> INFO: scanning low vcal = 200
[14:14:40.167] <TB0> INFO: Expecting 41600 events.
[14:14:44.161] <TB0> INFO: 41600 events read in total (3402ms).
[14:14:44.162] <TB0> INFO: Test took 4271ms.
[14:14:44.166] <TB0> INFO: scanning low vcal = 210
[14:14:44.443] <TB0> INFO: Expecting 41600 events.
[14:14:48.475] <TB0> INFO: 41600 events read in total (3440ms).
[14:14:48.475] <TB0> INFO: Test took 4309ms.
[14:14:48.479] <TB0> INFO: scanning low vcal = 220
[14:14:48.756] <TB0> INFO: Expecting 41600 events.
[14:14:52.750] <TB0> INFO: 41600 events read in total (3402ms).
[14:14:52.750] <TB0> INFO: Test took 4271ms.
[14:14:52.753] <TB0> INFO: scanning low vcal = 230
[14:14:53.030] <TB0> INFO: Expecting 41600 events.
[14:14:57.005] <TB0> INFO: 41600 events read in total (3383ms).
[14:14:57.006] <TB0> INFO: Test took 4252ms.
[14:14:57.009] <TB0> INFO: scanning low vcal = 240
[14:14:57.286] <TB0> INFO: Expecting 41600 events.
[14:15:01.304] <TB0> INFO: 41600 events read in total (3427ms).
[14:15:01.306] <TB0> INFO: Test took 4296ms.
[14:15:01.311] <TB0> INFO: scanning low vcal = 250
[14:15:01.586] <TB0> INFO: Expecting 41600 events.
[14:15:05.577] <TB0> INFO: 41600 events read in total (3400ms).
[14:15:05.578] <TB0> INFO: Test took 4267ms.
[14:15:05.583] <TB0> INFO: scanning high vcal = 30 (= 210 in low range)
[14:15:05.859] <TB0> INFO: Expecting 41600 events.
[14:15:09.842] <TB0> INFO: 41600 events read in total (3391ms).
[14:15:09.843] <TB0> INFO: Test took 4260ms.
[14:15:09.847] <TB0> INFO: scanning high vcal = 50 (= 350 in low range)
[14:15:10.123] <TB0> INFO: Expecting 41600 events.
[14:15:14.089] <TB0> INFO: 41600 events read in total (3375ms).
[14:15:14.090] <TB0> INFO: Test took 4242ms.
[14:15:14.095] <TB0> INFO: scanning high vcal = 70 (= 490 in low range)
[14:15:14.370] <TB0> INFO: Expecting 41600 events.
[14:15:18.346] <TB0> INFO: 41600 events read in total (3385ms).
[14:15:18.347] <TB0> INFO: Test took 4252ms.
[14:15:18.351] <TB0> INFO: scanning high vcal = 90 (= 630 in low range)
[14:15:18.627] <TB0> INFO: Expecting 41600 events.
[14:15:22.615] <TB0> INFO: 41600 events read in total (3396ms).
[14:15:22.616] <TB0> INFO: Test took 4265ms.
[14:15:22.620] <TB0> INFO: scanning high vcal = 200 (= 1400 in low range)
[14:15:22.945] <TB0> INFO: Expecting 41600 events.
[14:15:26.897] <TB0> INFO: 41600 events read in total (3360ms).
[14:15:26.898] <TB0> INFO: Test took 4278ms.
[14:15:27.458] <TB0> INFO: PixTestGainPedestal::measure() done
[14:16:10.962] <TB0> INFO: PixTestGainPedestal::fit() done
[14:16:10.962] <TB0> INFO: non-linearity mean: 0.939 0.982 0.925 0.982 0.982 0.984 0.943 0.938 0.982 0.973 0.979 0.953 0.948 0.945 0.942 1.031
[14:16:10.962] <TB0> INFO: non-linearity RMS: 0.060 0.005 0.094 0.003 0.003 0.003 0.055 0.070 0.003 0.182 0.005 0.122 0.108 0.122 0.143 0.147
[14:16:10.962] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C0.dat
[14:16:10.979] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C1.dat
[14:16:10.992] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C2.dat
[14:16:11.005] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C3.dat
[14:16:11.018] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C4.dat
[14:16:11.030] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C5.dat
[14:16:11.043] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C6.dat
[14:16:11.056] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C7.dat
[14:16:11.069] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C8.dat
[14:16:11.082] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C9.dat
[14:16:11.095] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C10.dat
[14:16:11.108] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C11.dat
[14:16:11.121] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C12.dat
[14:16:11.134] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C13.dat
[14:16:11.146] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C14.dat
[14:16:11.159] <TB0> INFO: write gain/ped parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//phCalibrationFitErr35_C15.dat
[14:16:11.172] <TB0> INFO: PixTestGainPedestal::fullTest() done, duration: 171 seconds
[14:16:11.172] <TB0> INFO: Decoding statistics:
[14:16:11.172] <TB0> INFO: General information:
[14:16:11.172] <TB0> INFO: 16bit words read: 3290278
[14:16:11.172] <TB0> INFO: valid events total: 332800
[14:16:11.172] <TB0> INFO: empty events: 1482
[14:16:11.172] <TB0> INFO: valid events with pixels: 331318
[14:16:11.172] <TB0> INFO: valid pixel hits: 646739
[14:16:11.172] <TB0> INFO: Event errors: 0
[14:16:11.172] <TB0> INFO: start marker: 0
[14:16:11.172] <TB0> INFO: stop marker: 0
[14:16:11.172] <TB0> INFO: overflow: 0
[14:16:11.172] <TB0> INFO: invalid 5bit words: 0
[14:16:11.173] <TB0> INFO: invalid XOR eye diagram: 0
[14:16:11.173] <TB0> INFO: frame (failed synchr.): 0
[14:16:11.173] <TB0> INFO: idle data (no TBM trl): 0
[14:16:11.173] <TB0> INFO: no data (only TBM hdr): 0
[14:16:11.173] <TB0> INFO: TBM errors: 0
[14:16:11.173] <TB0> INFO: flawed TBM headers: 0
[14:16:11.173] <TB0> INFO: flawed TBM trailers: 0
[14:16:11.173] <TB0> INFO: event ID mismatches: 0
[14:16:11.173] <TB0> INFO: ROC errors: 0
[14:16:11.173] <TB0> INFO: missing ROC header(s): 0
[14:16:11.173] <TB0> INFO: misplaced readback start: 0
[14:16:11.173] <TB0> INFO: Pixel decoding errors: 0
[14:16:11.173] <TB0> INFO: pixel data incomplete: 0
[14:16:11.173] <TB0> INFO: pixel address: 0
[14:16:11.173] <TB0> INFO: pulse height fill bit: 0
[14:16:11.173] <TB0> INFO: buffer corruption: 0
[14:16:11.188] <TB0> INFO: Decoding statistics:
[14:16:11.188] <TB0> INFO: General information:
[14:16:11.188] <TB0> INFO: 16bit words read: 3419702
[14:16:11.189] <TB0> INFO: valid events total: 353536
[14:16:11.189] <TB0> INFO: empty events: 19714
[14:16:11.189] <TB0> INFO: valid events with pixels: 333822
[14:16:11.189] <TB0> INFO: valid pixel hits: 649243
[14:16:11.189] <TB0> INFO: Event errors: 0
[14:16:11.189] <TB0> INFO: start marker: 0
[14:16:11.189] <TB0> INFO: stop marker: 0
[14:16:11.189] <TB0> INFO: overflow: 0
[14:16:11.189] <TB0> INFO: invalid 5bit words: 0
[14:16:11.189] <TB0> INFO: invalid XOR eye diagram: 0
[14:16:11.189] <TB0> INFO: frame (failed synchr.): 0
[14:16:11.189] <TB0> INFO: idle data (no TBM trl): 0
[14:16:11.189] <TB0> INFO: no data (only TBM hdr): 0
[14:16:11.189] <TB0> INFO: TBM errors: 0
[14:16:11.189] <TB0> INFO: flawed TBM headers: 0
[14:16:11.189] <TB0> INFO: flawed TBM trailers: 0
[14:16:11.189] <TB0> INFO: event ID mismatches: 0
[14:16:11.189] <TB0> INFO: ROC errors: 0
[14:16:11.189] <TB0> INFO: missing ROC header(s): 0
[14:16:11.189] <TB0> INFO: misplaced readback start: 0
[14:16:11.189] <TB0> INFO: Pixel decoding errors: 0
[14:16:11.189] <TB0> INFO: pixel data incomplete: 0
[14:16:11.189] <TB0> INFO: pixel address: 0
[14:16:11.189] <TB0> INFO: pulse height fill bit: 0
[14:16:11.189] <TB0> INFO: buffer corruption: 0
[14:16:11.189] <TB0> INFO: enter test to run
[14:16:11.189] <TB0> INFO: test: trim80 no parameter change
[14:16:11.189] <TB0> INFO: running: trim80
[14:16:11.190] <TB0> INFO: ######################################################################
[14:16:11.190] <TB0> INFO: PixTestTrim80::doTest()
[14:16:11.190] <TB0> INFO: ######################################################################
[14:16:11.191] <TB0> INFO: ----------------------------------------------------------------------
[14:16:11.191] <TB0> INFO: PixTestTrim80::trimTest() ntrig = 8, vcal = 80
[14:16:11.191] <TB0> INFO: ----------------------------------------------------------------------
[14:16:11.231] <TB0> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:16:11.231] <TB0> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:16:11.245] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:16:11.245] <TB0> INFO: run 1 of 1
[14:16:11.494] <TB0> INFO: Expecting 5025280 events.
[14:16:39.967] <TB0> INFO: 689512 events read in total (27881ms).
[14:17:07.537] <TB0> INFO: 1374640 events read in total (55451ms).
[14:17:35.375] <TB0> INFO: 2057720 events read in total (83289ms).
[14:18:03.030] <TB0> INFO: 2740304 events read in total (110944ms).
[14:18:30.905] <TB0> INFO: 3422856 events read in total (138819ms).
[14:18:58.948] <TB0> INFO: 4103568 events read in total (166862ms).
[14:19:26.513] <TB0> INFO: 4784432 events read in total (194427ms).
[14:19:36.518] <TB0> INFO: 5025280 events read in total (204432ms).
[14:19:36.610] <TB0> INFO: Test took 205365ms.
[14:20:03.989] <TB0> INFO: ROC 0 VthrComp = 79
[14:20:03.989] <TB0> INFO: ROC 1 VthrComp = 75
[14:20:03.989] <TB0> INFO: ROC 2 VthrComp = 76
[14:20:03.989] <TB0> INFO: ROC 3 VthrComp = 70
[14:20:03.989] <TB0> INFO: ROC 4 VthrComp = 73
[14:20:03.989] <TB0> INFO: ROC 5 VthrComp = 69
[14:20:03.990] <TB0> INFO: ROC 6 VthrComp = 82
[14:20:03.990] <TB0> INFO: ROC 7 VthrComp = 79
[14:20:03.990] <TB0> INFO: ROC 8 VthrComp = 82
[14:20:03.990] <TB0> INFO: ROC 9 VthrComp = 83
[14:20:03.990] <TB0> INFO: ROC 10 VthrComp = 82
[14:20:03.990] <TB0> INFO: ROC 11 VthrComp = 83
[14:20:03.990] <TB0> INFO: ROC 12 VthrComp = 73
[14:20:03.990] <TB0> INFO: ROC 13 VthrComp = 75
[14:20:03.990] <TB0> INFO: ROC 14 VthrComp = 79
[14:20:03.990] <TB0> INFO: ROC 15 VthrComp = 75
[14:20:04.318] <TB0> INFO: Expecting 41600 events.
[14:20:08.237] <TB0> INFO: 41600 events read in total (3328ms).
[14:20:08.238] <TB0> INFO: Test took 4245ms.
[14:20:08.251] <TB0> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:20:08.251] <TB0> INFO: ---> dac: vcal name: TrimThr1 ntrig: 8 dacrange: 10 .. 160 (-1/-1) hits flags = 528 (plus default)
[14:20:08.265] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:20:08.265] <TB0> INFO: run 1 of 1
[14:20:08.590] <TB0> INFO: Expecting 5025280 events.
[14:20:37.215] <TB0> INFO: 688376 events read in total (28033ms).
[14:21:04.764] <TB0> INFO: 1371584 events read in total (55582ms).
[14:21:32.274] <TB0> INFO: 2053880 events read in total (83092ms).
[14:22:00.160] <TB0> INFO: 2733240 events read in total (110978ms).
[14:22:28.567] <TB0> INFO: 3408016 events read in total (139385ms).
[14:22:55.833] <TB0> INFO: 4082232 events read in total (166651ms).
[14:23:23.626] <TB0> INFO: 4756168 events read in total (194444ms).
[14:23:34.605] <TB0> INFO: 5025280 events read in total (205423ms).
[14:23:34.676] <TB0> INFO: Test took 206411ms.
[14:23:58.818] <TB0> INFO: roc 0 with ID = 0 has maximal Vcal 113.388 for pixel 14/5 mean/min/max = 95.61/77.789/113.431
[14:23:58.819] <TB0> INFO: roc 1 with ID = 1 has maximal Vcal 110.892 for pixel 0/42 mean/min/max = 94.3912/77.8566/110.926
[14:23:58.819] <TB0> INFO: roc 2 with ID = 2 has maximal Vcal 111.378 for pixel 21/79 mean/min/max = 94.7061/77.9275/111.485
[14:23:58.820] <TB0> INFO: roc 3 with ID = 3 has maximal Vcal 104.475 for pixel 51/77 mean/min/max = 88.9271/73.2466/104.608
[14:23:58.820] <TB0> INFO: roc 4 with ID = 4 has maximal Vcal 110.61 for pixel 4/79 mean/min/max = 93.7267/76.6732/110.78
[14:23:58.820] <TB0> INFO: roc 5 with ID = 5 has maximal Vcal 110.548 for pixel 26/10 mean/min/max = 92.2778/73.974/110.582
[14:23:58.821] <TB0> INFO: roc 6 with ID = 6 has maximal Vcal 111.2 for pixel 8/73 mean/min/max = 92.8094/74.172/111.447
[14:23:58.821] <TB0> INFO: roc 7 with ID = 7 has maximal Vcal 108.336 for pixel 2/64 mean/min/max = 93.221/77.9387/108.503
[14:23:58.822] <TB0> INFO: roc 8 with ID = 8 has maximal Vcal 107.688 for pixel 21/3 mean/min/max = 91.3987/75.1033/107.694
[14:23:58.822] <TB0> INFO: roc 9 with ID = 9 has maximal Vcal 109.522 for pixel 0/3 mean/min/max = 91.8959/74.2098/109.582
[14:23:58.822] <TB0> INFO: roc 10 with ID = 10 has maximal Vcal 111.001 for pixel 13/19 mean/min/max = 92.4503/73.6927/111.208
[14:23:58.823] <TB0> INFO: roc 11 with ID = 11 has maximal Vcal 111.736 for pixel 9/71 mean/min/max = 92.9342/74.0905/111.778
[14:23:58.823] <TB0> INFO: roc 12 with ID = 12 has maximal Vcal 111.641 for pixel 0/37 mean/min/max = 94.3768/76.5451/112.208
[14:23:58.823] <TB0> INFO: roc 13 with ID = 13 has maximal Vcal 109.281 for pixel 1/22 mean/min/max = 93.4118/77.4088/109.415
[14:23:58.824] <TB0> INFO: roc 14 with ID = 14 has maximal Vcal 110.032 for pixel 51/79 mean/min/max = 94.4171/78.5687/110.265
[14:23:58.824] <TB0> INFO: roc 15 with ID = 15 has maximal Vcal 108.925 for pixel 0/56 mean/min/max = 93.6081/78.2123/109.004
[14:23:58.826] <TB0> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:23:58.914] <TB0> INFO: Expecting 411648 events.
[14:24:08.365] <TB0> INFO: 411648 events read in total (8859ms).
[14:24:08.379] <TB0> INFO: Expecting 411648 events.
[14:24:17.739] <TB0> INFO: 411648 events read in total (8957ms).
[14:24:17.750] <TB0> INFO: Expecting 411648 events.
[14:24:27.099] <TB0> INFO: 411648 events read in total (8946ms).
[14:24:27.115] <TB0> INFO: Expecting 411648 events.
[14:24:36.445] <TB0> INFO: 411648 events read in total (8927ms).
[14:24:36.464] <TB0> INFO: Expecting 411648 events.
[14:24:45.831] <TB0> INFO: 411648 events read in total (8964ms).
[14:24:45.850] <TB0> INFO: Expecting 411648 events.
[14:24:55.169] <TB0> INFO: 411648 events read in total (8916ms).
[14:24:55.191] <TB0> INFO: Expecting 411648 events.
[14:25:04.635] <TB0> INFO: 411648 events read in total (9041ms).
[14:25:04.667] <TB0> INFO: Expecting 411648 events.
[14:25:13.856] <TB0> INFO: 411648 events read in total (8786ms).
[14:25:13.883] <TB0> INFO: Expecting 411648 events.
[14:25:23.065] <TB0> INFO: 411648 events read in total (8779ms).
[14:25:23.101] <TB0> INFO: Expecting 411648 events.
[14:25:32.558] <TB0> INFO: 411648 events read in total (9054ms).
[14:25:32.619] <TB0> INFO: Expecting 411648 events.
[14:25:41.916] <TB0> INFO: 411648 events read in total (8893ms).
[14:25:41.964] <TB0> INFO: Expecting 411648 events.
[14:25:51.197] <TB0> INFO: 411648 events read in total (8830ms).
[14:25:51.268] <TB0> INFO: Expecting 411648 events.
[14:26:00.784] <TB0> INFO: 411648 events read in total (9113ms).
[14:26:00.853] <TB0> INFO: Expecting 411648 events.
[14:26:10.038] <TB0> INFO: 411648 events read in total (8782ms).
[14:26:10.140] <TB0> INFO: Expecting 411648 events.
[14:26:19.406] <TB0> INFO: 411648 events read in total (8863ms).
[14:26:19.480] <TB0> INFO: Expecting 411648 events.
[14:26:29.029] <TB0> INFO: 411648 events read in total (9146ms).
[14:26:29.096] <TB0> INFO: Test took 150270ms.
[14:26:30.514] <TB0> INFO: ---> dac: vcal name: TrimThr2 ntrig: 8 dacrange: 0 .. 150 (-1/-1) hits flags = 528 (plus default)
[14:26:30.525] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:26:30.525] <TB0> INFO: run 1 of 1
[14:26:30.765] <TB0> INFO: Expecting 5025280 events.
[14:26:59.294] <TB0> INFO: 670008 events read in total (27929ms).
[14:27:26.867] <TB0> INFO: 1336640 events read in total (55502ms).
[14:27:53.890] <TB0> INFO: 2002216 events read in total (82525ms).
[14:28:21.365] <TB0> INFO: 2664976 events read in total (110000ms).
[14:28:49.141] <TB0> INFO: 3323448 events read in total (137776ms).
[14:29:16.590] <TB0> INFO: 3979768 events read in total (165225ms).
[14:29:44.379] <TB0> INFO: 4634808 events read in total (193014ms).
[14:30:00.486] <TB0> INFO: 5025280 events read in total (209121ms).
[14:30:00.571] <TB0> INFO: Test took 210046ms.
[14:30:22.320] <TB0> INFO: ---> TrimStepCorr4 extremal thresholds: 50.226958 .. 104.633970
[14:30:22.559] <TB0> INFO: Expecting 208000 events.
[14:30:32.311] <TB0> INFO: 208000 events read in total (9160ms).
[14:30:32.312] <TB0> INFO: Test took 9991ms.
[14:30:32.362] <TB0> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 8 dacrange: 40 .. 114 (-1/-1) hits flags = 528 (plus default)
[14:30:32.376] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:30:32.376] <TB0> INFO: run 1 of 1
[14:30:32.654] <TB0> INFO: Expecting 2496000 events.
[14:31:01.518] <TB0> INFO: 684592 events read in total (28273ms).
[14:31:29.789] <TB0> INFO: 1368432 events read in total (56544ms).
[14:31:57.886] <TB0> INFO: 2045800 events read in total (84641ms).
[14:32:16.670] <TB0> INFO: 2496000 events read in total (103425ms).
[14:32:16.713] <TB0> INFO: Test took 104337ms.
[14:32:37.730] <TB0> INFO: ---> TrimStepCorr2 extremal thresholds: 61.091903 .. 95.465010
[14:32:37.969] <TB0> INFO: Expecting 208000 events.
[14:32:47.904] <TB0> INFO: 208000 events read in total (9344ms).
[14:32:47.905] <TB0> INFO: Test took 10173ms.
[14:32:47.952] <TB0> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 8 dacrange: 51 .. 105 (-1/-1) hits flags = 528 (plus default)
[14:32:47.965] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:32:47.965] <TB0> INFO: run 1 of 1
[14:32:48.243] <TB0> INFO: Expecting 1830400 events.
[14:33:16.582] <TB0> INFO: 681088 events read in total (27747ms).
[14:33:44.569] <TB0> INFO: 1361376 events read in total (55735ms).
[14:34:04.543] <TB0> INFO: 1830400 events read in total (75708ms).
[14:34:04.585] <TB0> INFO: Test took 76620ms.
[14:34:22.276] <TB0> INFO: ---> TrimStepCorr1a extremal thresholds: 64.603927 .. 89.699786
[14:34:22.515] <TB0> INFO: Expecting 208000 events.
[14:34:32.520] <TB0> INFO: 208000 events read in total (9414ms).
[14:34:32.521] <TB0> INFO: Test took 10243ms.
[14:34:32.574] <TB0> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 8 dacrange: 54 .. 99 (-1/-1) hits flags = 528 (plus default)
[14:34:32.587] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:34:32.587] <TB0> INFO: run 1 of 1
[14:34:32.865] <TB0> INFO: Expecting 1530880 events.
[14:35:01.864] <TB0> INFO: 695584 events read in total (28407ms).
[14:35:31.015] <TB0> INFO: 1389368 events read in total (57558ms).
[14:35:37.154] <TB0> INFO: 1530880 events read in total (63698ms).
[14:35:37.184] <TB0> INFO: Test took 64598ms.
[14:35:55.507] <TB0> INFO: ---> TrimStepCorr1b extremal thresholds: 67.676554 .. 89.699786
[14:35:55.762] <TB0> INFO: Expecting 208000 events.
[14:36:05.665] <TB0> INFO: 208000 events read in total (9311ms).
[14:36:05.666] <TB0> INFO: Test took 10157ms.
[14:36:05.713] <TB0> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 8 dacrange: 57 .. 99 (-1/-1) hits flags = 528 (plus default)
[14:36:05.726] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:36:05.726] <TB0> INFO: run 1 of 1
[14:36:06.004] <TB0> INFO: Expecting 1431040 events.
[14:36:35.192] <TB0> INFO: 685984 events read in total (28596ms).
[14:37:03.306] <TB0> INFO: 1371392 events read in total (56710ms).
[14:37:06.184] <TB0> INFO: 1431040 events read in total (59588ms).
[14:37:06.213] <TB0> INFO: Test took 60487ms.
[14:37:25.881] <TB0> INFO: ---> TrimThrFinal extremal thresholds: 60 .. 100
[14:37:25.881] <TB0> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 8 dacrange: 60 .. 100 (-1/-1) hits flags = 528 (plus default)
[14:37:25.895] <TB0> INFO: dacScan split into 1 runs with ntrig = 8
[14:37:25.895] <TB0> INFO: run 1 of 1
[14:37:26.140] <TB0> INFO: Expecting 1364480 events.
[14:37:54.810] <TB0> INFO: 668256 events read in total (28078ms).
[14:38:23.019] <TB0> INFO: 1335848 events read in total (56287ms).
[14:38:24.604] <TB0> INFO: 1364480 events read in total (57872ms).
[14:38:24.630] <TB0> INFO: Test took 58736ms.
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C0.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C1.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C2.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C3.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C4.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C5.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C6.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C7.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C8.dat
[14:38:41.363] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C9.dat
[14:38:41.364] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C10.dat
[14:38:41.364] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C11.dat
[14:38:41.364] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C12.dat
[14:38:41.364] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C13.dat
[14:38:41.364] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C14.dat
[14:38:41.364] <TB0> INFO: write dac parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//dacParameters80_C15.dat
[14:38:41.364] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C0.dat
[14:38:41.372] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C1.dat
[14:38:41.377] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C2.dat
[14:38:41.382] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C3.dat
[14:38:41.387] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C4.dat
[14:38:41.392] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C5.dat
[14:38:41.396] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C6.dat
[14:38:41.401] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C7.dat
[14:38:41.406] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C8.dat
[14:38:41.411] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C9.dat
[14:38:41.416] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C10.dat
[14:38:41.420] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C11.dat
[14:38:41.425] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C12.dat
[14:38:41.429] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C13.dat
[14:38:41.434] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C14.dat
[14:38:41.439] <TB0> INFO: write trim parameters into /home/l_tester/david/FullQualification/data/M1082_FullQualification_2016-10-31_10h24m_1477905852//003_FulltestTrim80_p17//trimParameters80_C15.dat
[14:38:41.444] <TB0> INFO: PixTestTrim80::trimTest() done
[14:38:41.444] <TB0> INFO: vtrim: 126 104 108 79 100 101 113 108 111 109 104 108 98 106 97 105
[14:38:41.444] <TB0> INFO: vthrcomp: 79 75 76 70 73 69 82 79 82 83 82 83 73 75 79 75
[14:38:41.444] <TB0> INFO: vcal mean: 79.99 79.98 80.02 79.94 79.96 80.00 79.99 79.97 79.94 79.96 79.94 79.92 79.93 79.97 79.96 79.98
[14:38:41.444] <TB0> INFO: vcal RMS: 0.80 0.73 0.74 0.73 0.74 0.78 0.77 0.75 0.76 0.75 0.80 0.83 0.73 0.74 0.71 0.69
[14:38:41.444] <TB0> INFO: bits mean: 9.64 9.55 9.11 10.22 9.26 10.17 10.15 9.50 10.30 10.00 10.20 9.85 9.37 9.66 8.66 9.03
[14:38:41.444] <TB0> INFO: bits RMS: 2.09 2.15 2.32 2.70 2.47 2.41 2.39 2.27 2.24 2.49 2.38 2.50 2.38 2.19 2.44 2.33
[14:38:41.450] <TB0> INFO: ----------------------------------------------------------------------
[14:38:41.450] <TB0> INFO: PixTestTrim80::trimBitTest() ntrig = 5, vtrims = 254 126 63 32
[14:38:41.450] <TB0> INFO: ----------------------------------------------------------------------
[14:38:41.453] <TB0> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 5 dacrange: 0 .. 199 (-1/-1) hits flags = 528 (plus default)
[14:38:41.468] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:38:41.468] <TB0> INFO: run 1 of 1
[14:38:41.704] <TB0> INFO: Expecting 4160000 events.
[14:39:14.862] <TB0> INFO: 773960 events read in total (32566ms).
[14:39:47.606] <TB0> INFO: 1540780 events read in total (65310ms).
[14:40:20.027] <TB0> INFO: 2301930 events read in total (97731ms).
[14:40:52.226] <TB0> INFO: 3059385 events read in total (129930ms).
[14:41:23.947] <TB0> INFO: 3812570 events read in total (161651ms).
[14:41:39.434] <TB0> INFO: 4160000 events read in total (177138ms).
[14:41:39.505] <TB0> INFO: Test took 178038ms.
[14:42:04.692] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 5 dacrange: 0 .. 215 (-1/-1) hits flags = 528 (plus default)
[14:42:04.705] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:42:04.705] <TB0> INFO: run 1 of 1
[14:42:04.941] <TB0> INFO: Expecting 4492800 events.
[14:42:36.926] <TB0> INFO: 726550 events read in total (31394ms).
[14:43:07.953] <TB0> INFO: 1447460 events read in total (62421ms).
[14:43:39.411] <TB0> INFO: 2165935 events read in total (93879ms).
[14:44:10.730] <TB0> INFO: 2880795 events read in total (125198ms).
[14:44:42.126] <TB0> INFO: 3592715 events read in total (156594ms).
[14:45:13.617] <TB0> INFO: 4303115 events read in total (188085ms).
[14:45:22.038] <TB0> INFO: 4492800 events read in total (196506ms).
[14:45:22.132] <TB0> INFO: Test took 197427ms.
[14:45:53.305] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[14:45:53.318] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:45:53.318] <TB0> INFO: run 1 of 1
[14:45:53.555] <TB0> INFO: Expecting 4305600 events.
[14:46:26.226] <TB0> INFO: 738905 events read in total (32079ms).
[14:46:57.374] <TB0> INFO: 1471255 events read in total (63227ms).
[14:47:29.183] <TB0> INFO: 2200565 events read in total (95036ms).
[14:48:00.741] <TB0> INFO: 2926675 events read in total (126594ms).
[14:48:32.109] <TB0> INFO: 3647845 events read in total (157962ms).
[14:49:01.096] <TB0> INFO: 4305600 events read in total (186949ms).
[14:49:01.223] <TB0> INFO: Test took 187905ms.
[14:49:35.782] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 5 dacrange: 0 .. 207 (-1/-1) hits flags = 528 (plus default)
[14:49:35.796] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:49:35.796] <TB0> INFO: run 1 of 1
[14:49:36.120] <TB0> INFO: Expecting 4326400 events.
[14:50:08.911] <TB0> INFO: 737640 events read in total (32199ms).
[14:50:40.693] <TB0> INFO: 1469200 events read in total (63981ms).
[14:51:12.381] <TB0> INFO: 2197845 events read in total (95669ms).
[14:51:43.897] <TB0> INFO: 2922855 events read in total (127185ms).
[14:52:15.642] <TB0> INFO: 3642815 events read in total (158930ms).
[14:52:45.795] <TB0> INFO: 4326400 events read in total (189083ms).
[14:52:45.900] <TB0> INFO: Test took 190105ms.
[14:53:13.200] <TB0> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 5 dacrange: 0 .. 206 (-1/-1) hits flags = 528 (plus default)
[14:53:13.214] <TB0> INFO: dacScan split into 1 runs with ntrig = 5
[14:53:13.214] <TB0> INFO: run 1 of 1
[14:53:13.494] <TB0> INFO: Expecting 4305600 events.
[14:53:46.360] <TB0> INFO: 739160 events read in total (32274ms).
[14:54:18.690] <TB0> INFO: 1471725 events read in total (64604ms).
[14:54:51.130] <TB0> INFO: 2201670 events read in total (97044ms).
[14:55:23.795] <TB0> INFO: 2928430 events read in total (129709ms).
[14:55:56.333] <TB0> INFO: 3650380 events read in total (162247ms).
[14:56:25.508] <TB0> INFO: 4305600 events read in total (191422ms).
[14:56:25.654] <TB0> INFO: Test took 192440ms.
[14:56:50.353] <TB0> INFO: PixTestTrim80::trimBitTest() done
[14:56:50.354] <TB0> INFO: PixTestTrim80::doTest() done, duration: 2439 seconds
[14:56:50.983] <TB0> INFO: enter test to run
[14:56:50.983] <TB0> INFO: test: exit no parameter change
[14:56:51.179] <TB0> QUIET: Connection to board 71 closed.
[14:56:51.179] <TB0> INFO: pXar: this is the end, my friend